EDD2516AKTA-5C-E ELPIDA [Elpida Memory], EDD2516AKTA-5C-E Datasheet - Page 24

• Manufacturer Part Number: EDD2516AKTA-5C-E
• Description: 256M bits DDR SDRAM (16M words x16 bits, DDR400)
• Manufacturer: ELPIDA [Elpida Memory]

Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge
of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low
period of DQS is referred as write postamble.
Data Sheet E0638E20 (Ver. 2.0)
Command
DQS
DQ
Address
/CK
CL = 3
CK
Command
NOP
DQS
/CK
t0
DQ
CK
Row
ACT
READ
t1
BL = 2
BL = 4
BL = 8
t0
NOP
t0.5
tRCD
Read Operation (/CAS Latency)
t1
tWPRES
WRITE
Column
tn tn+0.5 tn+1
t1.5
tRPRE
Write Operation
tWPRE
tAC,tDQSCK
t2
in0
in0
in0
24
t2.5
in1
in1
in1
NOP
in2
in2
tn+2
t3
out0
in3
in3
tWPST
t3.5
in4 in5
tn+3
out1
t4
NOP
out2
EDD2516AKTA-5-E
t4.5
in6
tn+4
out3
in7
t5
tRPST
tn+5
t5.5
BL: Burst length
VTT
VTT