EDD2516AKTA-7A-E ELPIDA [Elpida Memory], EDD2516AKTA-7A-E Datasheet
EDD2516AKTA-7A-E
Manufacturer Part Number
EDD2516AKTA-7A-E
Description
256M bits DDR SDRAM (16M words x 16 bits)
Manufacturer
ELPIDA [Elpida Memory]
Datasheet
1.EDD2516AKTA-7A-E.pdf
(49 pages)
Description
The EDD2516AKTA is a 256M bits Double Data Rate
(DDR) SDRAM organized as 4,194,304 words
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture.
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable.
TSOP (II).
Features
Document No. E0502E30 (Ver. 3.0)
Date Published September 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Power supply : VDDQ = 2.5V
Data rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
transitions
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
TSOP (II) package with lead free solder (Sn-Bi)
4 banks. Read and write operations are performed at
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
Commands entered on each positive CK edge; data
7.8 s maximum average periodic refresh interval
Auto refresh
Self refresh
RoHS compliant
: VDD = 2.5V
EDD2516AKTA-E (16M words 16 bits)
It is packaged in 66-pin plastic
Data strobe (DQS) both for
256M bits DDR SDRAM
0.2V
0.2V
DATA SHEET
16 bits
Pin Configurations
/xxx indicates active low signal.
A0 to A12
BA0, BA1
DQ0 to DQ15
UDQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
A10(AP)
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
LDQS
/CAS
/RAS
VDD
VDD
LDM
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/WE
BA0
BA1
/CS
NC
NC
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66-pin Plastic TSOP(II)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
(Top view)
Elpida Memory, Inc. 2004-2005
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
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