EDD2516KCTA-6BS-E ELPIDA [Elpida Memory], EDD2516KCTA-6BS-E Datasheet - Page 9

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EDD2516KCTA-6BS-E

Manufacturer Part Number
EDD2516KCTA-6BS-E
Description
256M bits DDR SDRAM with Super Self-Refresh
Manufacturer
ELPIDA [Elpida Memory]
Datasheet
Test Conditions
Parameter
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
Input differential voltage, CK and /CK
inputs
Input differential cross point voltage,
CK and /CK inputs
Input signal slew rate
Preliminary Data Sheet E0641E20 (Ver.2.0)
13. tDAL = (tWR/tCK)+(tRP/tCK)
14. When the memory is in “Exiting SSR” state, any command except SSR is ignored.
If SF pin is monitored by the system and as soon as it returns to low (tFHSSR), any command for IDLE
state will be accepted by the memory. (tSSREX is "Don't care" in this case. )
If SF pin is not monitored, tSSREX has to be satisfied. (Issue auto refresh command repeatedly at less
than 7.8μs interval during tSSREX.)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For -7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
/CK
CK
Measurement point
VID
Symbol
VREF
VTT
VIH (AC)
VIL (AC)
VID (AC)
VIX (AC)
SLEW
Input Waveforms and Output Load
DQ
VIL
SLEW = (VIH (AC) – VIL (AC))/Δt
tDAL = 5 clocks
tCL
Δt
tCK
9
VTT
VIX
VIH
RT = 50Ω
CL = 30pF
tCH
Value
VDDQ/2
VREF
VREF + 0.31
VREF − 0.31
0.62
VREF
1
VDD
VREF
VSS
VDD
VREF
VSS
EDD2516KCTA
Unit
V
V
V
V
V
V
V/ns

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