EDD5108ADTA-6BLI ELPIDA [Elpida Memory], EDD5108ADTA-6BLI Datasheet
EDD5108ADTA-6BLI
Related parts for EDD5108ADTA-6BLI
EDD5108ADTA-6BLI Summary of contents
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... DDR SDRAM WTR (Wide Temperature Range) EDD5108ADTA-LI (64M words 8 bits) EDD5116ADTA-LI (32M words 16 bits) Description The EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture ...
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... Ordering Information Mask Organization Part number version (words EDD5108ADTA-6BLI 64M 8 EDD5108ADTA-7ALI EDD5116ADTA-6BLI 32M 16 EDD5116ADTA-7ALI Part Number Elpida Memory Type D: Monolithic Device Product Code D: DDR SDRAM Density / Bank 51: 512M / 4-bank Bit Organization 08: x8 16: x16 Voltage, Interface A: 2.5V, SSTL_2 Die Rev ...
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... CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Electrical Specifications.................................................................................................................................4 Block Diagram .............................................................................................................................................10 Command Operation ...................................................................................................................................13 Simplified State Diagram .............................................................................................................................20 Operation of the DDR SDRAM ....................................................................................................................21 Timing Waveforms.......................................................................................................................................40 Package Drawing ........................................................................................................................................46 Recommended Soldering Conditions..........................................................................................................47 Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI 3 ...
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... VIN (DC) specifies the allowable DC execution of each differential input. 5. VID (DC) specifies the input differential voltage required for switching. 6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Symbol Rating VT –1.0 to +3.6 VDD – ...
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... Input leakage current ILI –2 Output leakage current ILO –5 Output high current IOH –15.2 Output low current IOL 15.2 Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI max Unit Test condition 150 150 CKE ≥ VIH, mA 135 135 tRC = tRC (min.) CKE ≥ VIH ...
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... DQS falling edge hold time from CK DQS input high pulse width DQS input low pulse width Address and control input setup time Address and control input hold time Address and control input pulse width Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Pins min. typ. CK, /CK 2.0 — ...
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... For each of the terms above, if not already an integer, round to the next highest integer. Example: For –7A Speed 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI -6B -7A min. max. ...
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... Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate CK VID /CK Measurement point Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Symbol Value VREF VDDQ/2 VTT VREF VIH (AC) VREF 0.31 VIL (AC) VREF ...
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... DM to data in latency Mode register set command cycle time Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Number of clock cycle 6ns 7.5ns Symbol min. max. ...
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... Block Diagram CK /CK CKE A0 to A12, BA0, BA1 Mode register /CS /RAS /CAS /WE Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit ...
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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Column address AY0 to AY9, AY11 AY0 to AY9 BA1 ...
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... DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI 12 ...
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... This command starts a write operation. The start address of the burst write is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI CKE Symbol n – ...
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... Power down Power down exit (PDEX) Remark: H: VIH. L: VIL. : VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI BA1 CKE n – 1 ...
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... Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Address Command Operation DESL NOP NOP NOP BST ILLEGAL* BA, CA, A10 READ/READA ILLEGAL* BA, CA, A10 WRIT/WRITA ILLEGAL* BA, RA ACT ILLEGAL* BA, A10 PRE, PALL NOP ILLEGAL ...
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... Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Address Command Operation DESL NOP NOP NOP BST BST Interrupting burst read BA, CA, A10 READ/READA operation to start new read BA, CA, A10 WRIT/WRITA ILLEGAL* BA, RA ACT ILLEGAL* ...
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... To command (different bank, non- From command interrupting command) Read w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Write w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Address Command Operation DESL NOP NOP NOP BST ILLEGAL BA, CA, A10 READ/READA ILLEGAL* ...
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... Remark: H: VIH. L: VIL. : VIH or VIL Note: Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Operation INVALID, CK (n-1) would exit self refresh Self refresh recovery ...
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... DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI 19 ...
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... POWER APPLIED ON PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO IDLE ...
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... BA0 BA1 A12 A11 A10 MRS CAS Latency A8 DLL Reset Yes Mode Register Set [MRS] (BA0 = 0, BA1 = 0) Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI (7) (8) PALL REF REF REF RFC 200 cycles (min ...
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... Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- Driver Strength 0 Normal 1 Weak Burst length = 4 Starting Ad. Addressing(decimal) ...
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... Command NOP ACT NOP Address Row DQS Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) ...
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... High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write postamble /CK tRCD Command NOP ACT NOP Row Address DQS Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI t1 t1.5 t2 t2.5 t3 t3.5 NOP tAC,tDQSCK out0 out1 out2 out3 tRPRE tAC,tDQSCK out0 out1 out2 Read Operation (/CAS Latency) tn tn+0.5 tn+1 ...
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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK READ Command DQS DQS CL = 2.5 DQ Burst Stop during a Read Operation Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI t1 t1.5 t2 t2.5 t3 t3.5 BST NOP tBSTZ 2 cycles out0 out1 tBSTZ 2.5 cycles out0 ...
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... Refer to ‘Function truth table and related notes (Notes.*14). CK /CK tRAS (min) tRCD (min) ACT NOP WRITA Command DM DQS DQ Note: Internal auto-precharge starts at the timing indicated by " Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI tRPD 2 cycles (= BL/2) READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP BL cycles in1 in2 ...
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... Bank0 Active READ to READ Command Interval (same ROW address in the same bank) Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Operation The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘ ...
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... CK /CK Command ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active READ to READ Command Interval (different bank) Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- READ READ NOP Column A Column B out out A0 A1 Column = A Column = B Read Read Bank0 ...
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... Bank0 Active WRITE to WRITE Command Interval (same ROW address in the same bank) Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Operation The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...
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... Command ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 30 tn+3 tn+4 ...
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... DQ High-Z DQS OUTPUT Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Operation Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...
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... DQS INPUT Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Operation To complete the burst operation, the consecutive read command should be performed tWRD (= BL after the write command. Precharge the bank tWRD after the preceding write command. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘ ...
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... DQS Data masked [WRITE to READ delay = 1 clock cycle] Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. ...
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... DM DQ in0 in1 DQS Data masked Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 3 clock cycle] Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- NOP CL=2 in2 in3 out0 out1 out2 out3 ...
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... READ to PRECHARGE Command Interval (same bank): To output all data ( CLK /CLK Command NOP NOP READ DQ DQS tRPD = BL/2 READ to PRECHARGE Command Interval (same bank): To output all data ( Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- PRE/ NOP PALL out0 out1 out2 out3 PRE/ NOP ...
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... READ to PRECHARGE Command Interval (same bank): To stop output data ( /CK Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- NOP PRE/PALL out0 out1 tHZP ...
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... In order to write the last input data, tWR (min) must be satisfied. When the precharge command is issued, the invalid data must be masked by DM /CK Command WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- PRE/PALL NOP tWPD tWR in2 in3 Last data input ...
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... MRS Address CODE Mode Register Set Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued ...
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... By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- Mask Mask Write mask latency = 0 ...
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... DQS DQ (Dout) Write Timing Definition tCK /CK CK tDQSS DQS tWPRES tWPRE DQ (Din) tDS DM tDS Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH tDIPW ...
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... A10 tIS tIH Address DM High-Z DQS High-Z DQ (output) Bank 0 Bank 0 Active Active Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI tRC tRAS tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...
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... A10 tIS tIH tIS tIH Address DQS (input (input) Bank 0 Bank 0 Bank 0 Active Active Write Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 42 tRP tIS tIH tIS tIH ...
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... If needed set Read/Write Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address R:a C:a DM DQS DQ (output) High-Z DQ (input) Bank 0 Bank 0 Active Read Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- tMRD Bank 3 Bank 3 Read Active R:b C tRWD Bank 3 Bank 3 Active Write 43 ...
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... Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- High-Z tRFC Auto Bank 0 Refresh Active Bank 0 Read VIH or VIL ...
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... CK tIS CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active Bank 0 Read VIH or VIL ...
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... PIN 0.65 0.17 to 0.32 0. 0.91 max. 0. Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA- Unit: mm 0.80 Nom 0.25 0.60 ± 0.15 ECA-TS2-0029-01 ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD51XXADTA. Type of Surface Mount Device EDD51XXADTA: 66-pin Plastic TSOP (II) Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI 47 ...
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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI 48 CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Data Sheet E0505E10 (Ver. 1.0) EDD5108ADTA-LI, EDD5116ADTA-LI 49 M01E0107 ...