EDD5108AGTA-5BLI-E ELPIDA [Elpida Memory], EDD5108AGTA-5BLI-E Datasheet
EDD5108AGTA-5BLI-E
Related parts for EDD5108AGTA-5BLI-E
EDD5108AGTA-5BLI-E Summary of contents
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... EDD5116AGTA-LI (32M words × 16 bits) Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • ...
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... Ordering Information Mask Organization Part number version (words × bits) EDD5108AGTA-5BLI-E G 64M × 8 EDD5108AGTA-5CLI-E EDD5108AGTA-6BLI-E EDD5108AGTA-7ALI-E EDD5108AGTA-7BLI-E EDD5116AGTA-5BLI-E 32M × 16 EDD5116AGTA-5CLI-E EDD5116AGTA-6BLI-E EDD5116AGTA-7ALI-E EDD5116AGTA-7BLI-E Part Number Elpida Memory Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank ...
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... DQS, LDQS, UDQS Input and output data strobe /CS Chip select /RAS Row address strobe /CAS Column address strobe /WE Write enable DM, UDM, LDM Input mask Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI 66-pin Plastic TSOP(II) VDD 1 66 VSS DQ0 2 65 DQ15 VDDQ 3 64 ...
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... CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Speed Grade Compatibility............................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................13 Pin Function.................................................................................................................................................14 Command Operation ...................................................................................................................................16 Simplified State Diagram .............................................................................................................................23 Operation of the DDR SDRAM ....................................................................................................................24 Timing Waveforms.......................................................................................................................................43 Package Drawing ........................................................................................................................................49 Recommended Soldering Conditions..........................................................................................................50 Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI 4 ...
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... VIN (DC) specifies the allowable DC execution of each differential input. 5. VID (DC) specifies the input differential voltage required for switching. 6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Symbol Rating VT –1.0 to +3.6 VDD – ...
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... Operating current IDD4R (Burst read operation) Operating current IDD4W (Burst write operation) Auto-refresh current IDD5 Self-refresh current IDD6 Operating current IDD7A (4 banks interleaving) Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI max. × 8 × 16 Grade Unit 100 100 mA 120 120 ...
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... Cdi1 Cdi2 Data input/output capacitance CI/O Delta input/output capacitance Cdio Notes: 1. These parameters are measured on conditions 100MHz, VOUT = VDDQ/2, ΔVOUT = 0.2V. 2. DOUT circuits are disabled. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI max. Unit Test condition 2 µA VDD ≥ VIN ≥ VSS 5 µA VDDQ ≥ ...
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... Precharge to active command period Active to Autoprecharge delay Active to active command period Write recovery time Auto precharge write recovery and precharge time Internal write to Read command delay Average periodic refresh interval Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI -5B -5C Symbol min. max. min. tCK 5 ...
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... Active to Active/Auto-refresh tRC command period Auto-refresh to Active/Auto-refresh tRFC command period Active to Read/Write delay tRCD Precharge to active command period tRP Active to Autoprecharge delay tRAP Active to active command period tRRD Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI -6B -7A min. max. min. max 7 ...
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... For each of the terms above, if not already an integer, round to the next highest integer. Example: For –5C Speed tCK = 5ns, tWR = 15ns and tRP= 18ns, tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4) tDAL = 7 clocks Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI -6B -7A min. max. ...
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... Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate CK VID /CK Measurement point Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Symbol Value VREF VDDQ/2 VTT VREF VIH (AC) VREF + 0.31 VREF − 0.31 VIL (AC) VID (AC) 0 ...
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... Active to Precharge command period tRAS Active to Active/Auto-refresh tRC command period Auto-refresh to Active/Auto-refresh tRFC command period Active to Read/Write delay tRCD Precharge to active command period tRP Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Number of clock cycle 5ns 6ns min. max. min. max BL BL/2 — ...
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... Block Diagram CK /CK CKE A0 to A12, BA0, BA1 Mode register /CS /RAS /CAS /WE Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit ...
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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Column address AY0 to AY9, AY11 AY0 to AY9 BA1 ...
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... DQ15) of write data. DQ0 to DQ15 (input/output pins) Data is input to and output from these pins (DQ0 to DQ7; EDD5108AGTA, DQ0 to DQ15; EDD5116AGTA). DQS, LDQS and UDQS (input and output pins) DQS provides the read data strobes (as output) and the write data strobes (as input). In ×16 products, LDQS is the lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal ...
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... This command starts a write operation. The start address of the burst write is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI CKE Symbol n – ...
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... Power down exit (PDEX) Remark: H: VIH. L: VIL. ×: VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI BA1 CKE n – ...
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... × Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Address Command Operation × DESL NOP × NOP NOP × BST ILLEGAL* BA, CA, A10 READ/READA ILLEGAL* BA, CA, A10 WRIT/WRITA ILLEGAL* BA, RA ACT ILLEGAL* ...
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... × Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Address Command Operation × DESL NOP × NOP NOP × BST BST Interrupting burst read BA, CA, A10 READ/READA operation to start new read BA, CA, A10 WRIT/WRITA ...
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... To command (different bank, non- From command interrupting command) Read w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Write w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Address Command Operation × DESL NOP × NOP NOP × BST ILLEGAL ...
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... Remark: H: VIH. L: VIL. ×: VIH or VIL Note: 1. Self-refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Operation × × × ...
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... After the exit, input auto-refresh command within 7.8 μs. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI To issue non-read commands, tSNR has ...
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... POWER APPLIED ON PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO ...
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... CK /CK Command PALL EMRS MRS 2 cycles (min.) 2 cycles (min.) 2 cycles (min.) DLL enable DLL reset with A8 = High Power-up Sequence after CKE Goes High Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI (7) (8) PALL REF REF REF RFC RFC Disable DLL reset with A8 = Low ...
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... Mode Register Set [MRS] (BA0 = 0, BA1 = 0) BA0 BA1 A12 A11 A10 EMRS Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0) Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- LMODE BT A3 Burst Type 0 0 Reserved ...
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... Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Burst length = 4 Starting Ad. Addressing(decimal) Interleave A1 A0 Sequence ...
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... Command NOP ACT NOP Address Row DQS Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) ...
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... High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write postamble /CK tRCD Command NOP ACT NOP Row Address DQS Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI t1 t1.5 t2 t2.5 t3 t3.5 t4 NOP tRPRE tAC,tDQSCK out0 out1 Read Operation (/CAS Latency) tn tn+0.5 tn+1 tn+2 tn+3 WRITE NOP ...
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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK READ Command DQS Burst Stop during a Read Operation Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI t1 t1.5 t2 t2.5 t3 t3.5 t4 BST NOP tBSTZ out0 out1 29 t4 ...
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... Command ACT NOP WRITA DM DQS DQ Note: Internal auto-precharge starts at the timing indicated by " Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Refer to ‘Function truth table and related tRPD BL/2 cycles READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge ...
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... Bank0 Active READ to READ Command Interval (same ROW address in the same bank) Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Operation The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘ ...
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... Command ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active READ to READ Command Interval (different bank) Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- READ READ NOP Column A Column B Column = A Column = B Read Read Bank0 Bank3 Read Read ...
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... Bank0 Active WRITE to WRITE Command Interval (same ROW address in the same bank) Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Operation The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...
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... Command ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 34 tn+3 ...
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... DM DQ High-Z DQS Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Operation Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...
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... DQS INPUT Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Operation To complete the burst operation, the consecutive read command should be performed tWRD (= 1 + BL/2 + tWTR) after the write command. ...
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... DQS Data masked [WRITE to READ delay = 1 clock cycle] Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. ...
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... DM DQ in0 in1 DQS Data masked Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 3 clock cycle] Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- NOP CL=3 in2 in3 out0 out1 out2 out3 ...
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... CL) after the precharge command /CK Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- PRE/ NOP PALL out0 out1 out2 out3 ...
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... In order to write the last input data, tWR (min) must be satisfied. When the precharge command is issued, the invalid data must be masked by DM /CK Command WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- NOP tWPD tWR in2 in3 Last data input ...
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... Address CODE Mode Register Set Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued ...
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... Notes: 1. Device must be in the “All banks idle” state prior to entering self-refresh mode. 2. tSRD is applied for a read or a read with autoprecharge command. 3. tSNR is applied for any command except a read or a read with autoprecharge command. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- ...
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... DQS DQ (Dout) Write Timing Definition tCK /CK CK tDQSS DQS tWPRES tWPRE DQ (Din) tDS DM tDS Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH ...
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... A10 tIS tIH Address DM High-Z DQS High-Z DQ (output) Bank 0 Bank 0 Active Active Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI tRC tRAS tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...
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... A10 tIS tIH tIS tIH Address DQS (input (input) Bank 0 Bank 0 Bank 0 Active Active Write Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 45 tRP tIS tIH tIS tIH ...
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... Read/Write Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address R:a C:a DM DQS DQ (output) High-Z DQ (input) Bank 0 Bank 0 Active Read Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- tMRD Bank 3 Bank 3 Bank 3 Read Precharge Active R:b C tRWD Bank 3 Bank 3 ...
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... Auto-Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- High-Z tRFC Auto Bank 0 Refresh Active Bank 0 Read VIH or VIL ...
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... CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active Bank 0 Read VIH or VIL ...
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... 0.91 max. 0. Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- 8° 49 Unit: mm 0.80 Nom 0.25 +0.15 0.60 −0.20 ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD5108AGTA, EDD5116AGTA. Type of Surface Mount Device EDD5108AGTA, EDD5116AGTA: 66-pin Plastic TSOP (II) < Lead free (Sn-Bi) > Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI 50 ...
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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA-LI 51 CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E1304E10 (Ver. 1.0) EDD5108AGTA-LI, EDD5116AGTA- ...