HT48R70A-1_07 HOLTEK [Holtek Semiconductor Inc], HT48R70A-1_07 Datasheet
HT48R70A-1_07
Related parts for HT48R70A-1_07
HT48R70A-1_07 Summary of contents
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... Watchdog Timer 8192 16 program memory ROM General Description The HT48R70A-1/HT48C70-1 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48C70-1 is fully pin and functionally compatible with the OTP version HT48R70A-1 device ...
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... Block Diagram Rev. 2.10 HT48R70A-1/HT48C70-1 2 August 7, 2007 ...
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... I/O Pull-high* RES I VDD Rev. 2.10 HT48R70A-1/HT48C70-1 Description Bidirectional 8-bit input/output ports Each bit can be configured as a wake-up input by options. Software instruc- tions determine the CMOS output or Schmitt trigger or CMOS input with or with- out pull high resistor (by options). Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or Schmitt trigger input (pull-high depends on options) ...
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... STB1 I Standby Current (WDT Disabled RTC Off) STB2 Rev. 2.10 HT48R70A-1/HT48C70-1 Description OSC1 and OSC2 are connected network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. These two pins also can be optioned as an RTC oscillator (32768Hz). In this case, the system clock comes from an internal RC oscillator whose fre- quency has 4 options (3 ...
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... Watchdog Time-out Period (System Clock) WDT2 t Watchdog Time-out Period (RTC OSC) WDT3 t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT Rev. 2.10 HT48R70A-1/HT48C70-1 Test Conditions Min. Typ. V Conditions load, system HALT 0.9V DD enabled 2 ...
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... S12 S11 S10 Note: *12~*0: Program counter bits #12~#0: Instruction code bits Rev. 2.10 HT48R70A-1/HT48C70-1 incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading register, subroutine call or return from ...
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... Note: *12~*0: Table location bits @7~@0: Table pointer bits Rev. 2.10 HT48R70A-1/HT48C70-1 Program Memory the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has ...
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... Writing indirectly results in no operation. The memory pointer registers (MP0 and MP1) are 8-bit registers. Rev. 2.10 HT48R70A-1/HT48C70-1 RAM Mapping Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations ...
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... WDT time-out Unused bit, read as 0 Rev. 2.10 HT48R70A-1/HT48C70-1 Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded ...
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... If only one stack is left and enabling the interrupt is not Rev. 2.10 HT48R70A-1/HT48C70-1 Function INTC (0BH) Register well controlled, the original control sequence will be dam- aged once the CALL operates in the interrupt subrou- tine ...
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... If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscil- lator (RTC OSC) is strongly recommended, since the HALT will stop the system clock. Rev. 2.10 HT48R70A-1/HT48C70-1 WS2 WS1 WS0 ...
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... By examining the PDF and TO flags, the program can distinguish between different chip resets . Rev. 2.10 HT48R70A-1/HT48C70-1 Reset Timing Chart Note: Most applications can use the Basic Reset Cir- cuit as shown, however for applications with ex- tensive noise recommended to use the Hi-noise Reset Circuit ...
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... PFC 1111 1111 PG 1111 1111 PGC 1111 1111 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 2.10 HT48R70A-1/HT48C70-1 RES Reset (Normal Operation) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 00-0 1--- 00-0 1--- xxxx xxxx xxxx xxxx xxxx xxxx ...
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... T1M1 11=Pulse width measurement mode 00=Unused Rev. 2.10 HT48R70A-1/HT48C70-1 There are 3 registers related to the Timer/Event Counter 0;TMR0H ([0CH]), TMR0L ([0DH]), TMR0C ([0EH]). Writ- ing TMR0L will only put the written data to an internal lower-order byte buffer (8 bits) and writing TMR0H will ...
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... TMR0/TMR1 returns to the original level and resets the T0ON/T1ON. The measured result will remain in the Timer/Event Counter 0/1 even if the Rev. 2.10 HT48R70A-1/HT48C70-1 activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the T0ON/T1ON, the cycle measurement will function again as long as it receives further transient pulse ...
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... For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H, 1BH, 1DH and 1FH. Rev. 2.10 HT48R70A-1/HT48C70-1 After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high op- tions). Each bit of these input/output latches can be set or cleared by SET [m] ...
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... Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. Rev. 2.10 HT48R70A-1/HT48C70 ...
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... PA, PB, PC, PD, PE, PF, PG pull-high enable or disable (By port) System oscillator 8 Ext. RC, Ext. crystal, Int. RC+RTC 9 Int. RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz 10 LVR enable or disable 11 BZ/BZ enable or disable Rev. 2.10 HT48R70A-1/HT48C70-1 Options /4 or RTC oscillator or disable SYS /4 or RTCOSC SYS /4 or RTCOSC SYS 18 August 7, 2007 ...
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... RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external com- ponents, refer to Application Note HA0075E for more information. Rev. 2.10 HT48R70A-1/HT48C70-1 19 August 7, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 2.10 HT48R70A-1/HT48C70-1 Description 20 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 2.10 HT48R70A-1/HT48C70-1 Description 21 Instruction Flag Cycle Affected 2 None ...
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... Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF PDF PDF ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF PDF addr PDF OV Z ...
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... Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF PDF OV ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 Program Counter+1 PDF PDF PDF ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF Program Counter+1 ...
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... Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 Stack PDF Stack PDF ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF OV Z ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF PDF ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF PDF ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 2.10 HT48R70A-1/HT48C70-1 PDF PDF PDF ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions Symbol Rev. 2.10 HT48R70A-1/HT48C70-1 Dimensions in mil Min. Nom. 395 291 8 613 Max. 420 299 12 637 August 7, 2007 ...
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... QFP (14´20) Outline Dimensions Symbol Rev. 2.10 HT48R70A-1/HT48C70-1 Dimensions in mm Min. Nom. 18.80 13.90 24.80 19.90 1 0.40 2.50 0.10 1.15 0. Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.45 0.20 7 August 7, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.10 HT48R70A-1/HT48C70-1 Dimensions in mm 330 1.0 100 0.1 13.0+0.5 0.2 2.0 0.5 32.2+0.3 0.2 38.2 0.2 37 August 7, 2007 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.10 HT48R70A-1/HT48C70-1 Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.1 14.2 0.1 2.0 Min. 1.5+0.25 4.0 0.1 2.0 0.1 12.0 0.1 16.20 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 38 August 7, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.10 HT48R70A-1/HT48C70-1 39 August 7, 2007 ...