V53C16256 Mosel Vitelic Corp, V53C16256 Datasheet
V53C16256
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V53C16256 Summary of contents
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... Description The V53C16256H is a 262,144 x 16 bit high- performance CMOS dynamic random access mem- ory. The V53C16256H offers Fast Page mode with dual CAS inputs. An address, CAS and RAS input capacitances are reduced to one quarter when the x4 DRAM is used to construct the same memory density ...
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... Column Address Strobe Lower Byte Control WE Write Enable OE Output Enable I/O –I/O Data Input, Output +5V Supply Supply Connect V53C16256H Rev. 2.3 June 1998 FAMILY DEVICE K (SOJ) T (TSOP-II) 40/44 Pin Plastic TSOP-II PIN CONFIGURATION Vss Vcc I/O16 ...
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... UCAS LCAS RAS RAS CLOCK GENERATOR REFRESH COUNTER • • • V53C16256H Rev. 2.3 June 1998 Capacitance ° Symbol Parameter C Address Input IN1 C RAS, UCAS, LCAS, IN2 WE Data Input/Output OUT * Note: Capacitance is sampled and not 100% tested ...
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... Supply Current, CC6 CC CMOS Standby V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V53C16256H Rev. 2.3 June 1998 (1- unless otherwise specified. SS V53C16256H Access Time Min. Typ. Max. –10 10 – 200 35 190 40 180 ...
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... CAS Access Time from RL1QV RAC RAS Access Time from AVQV CAA Column Address V53C16256H Rev. 2.3 June 1998 = 0V unless otherwise noted Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 30 75K 35 75K ...
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... CL1WL2 CWD RAS to WE Delay RL1WL2 RWD in Read-Modify- Write Cycle CAS Pulse Width CL1CH1 CRW (RMW) V53C16256H Rev. 2.3 June 1998 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max ...
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... PCM (RMW) Read-Modify-Write Cycle Time Transition Time T T (Rise and Fall Refresh Interval REF (512 Cycles) V53C16256H Rev. 2.3 June 1998 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max ...
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... Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. V53C16256H Rev. 2.3 June 1998 (max.) is measured with a maximum of two CC (min.) may undershoot to – ...
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... Hidden Refresh Read L®H®L RAS-Only Refresh L CBR Refresh H®L Notes: 1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. 3. Only one of the two CAS must be active (LCAS or UCAS). V53C16256H Rev. 2.3 June 1998 LCAS UCAS WE OE ADDRESS ...
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... UCAS, LCAS ASR ( ADDRESS ROW ADDRESS I V53C16256H Rev. 2.3 June 1998 t RC (2) t RAS ( (23) t CSH ( RCD (6) RSH (R)(12) t CAS (5) t RAD (24 RAH (9) CAH (11) t ASC (10) COLUMN ADDRESS t CAR (44) ...
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... V IH ROW ADDRESS ADDRESS RAD (24 I V53C16256H Rev. 2.3 June 1998 t RC (2) t RAS ( (23) t CSH ( RCD (6) RSH (W)(12) t CAS ( RAD (24) CAR (44 CAH (11) RAH (9) t ASC (10) COLUMN ADDRESS t CWL (26) ...
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... ADDRESS ADD RAD (24) t WCS (27 (32 I/O DATA V53C16256H Rev. 2.3 June 1998 t RAS ( (23 RCD (6) PC (42 (43 CAS (5) CAS (5) t CSH (4) t RAH (9) t ASC (10) COLUMN COLUMN ADDRESS ADDRESS t ...
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... Waveforms of RAS-Only Refresh Cycle V IH RAS CRP (13 CAS ASR ( ADDRESS ROW ADDR Don’t care NOTE: V53C16256H Rev. 2.3 June 1998 t RAS (1) t CSH (4) t PCM (50 (43 CAS (5) CAS ( ASC (10) ASC (10 CAH (11) CAH (11) COLUMN COLUMN ...
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... V IH RAS RPC (48 (43 CAS (22 I NOTE: WE, OE, A –A = Don’t care 8 0 V53C16256H Rev. 2.3 June 1998 t RAS ( CHR (49) CP (43 RCS ( (21 WCS (27) WCH (28 (32) DH (33 (2) t RAS (1) t ...
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... V IH ROW ADDRESS ADD WCS (27 (32 I V53C16256H Rev. 2.3 June 1998 RAS ( (23 RSH (R)(12) CHR (49) t RAD (24) t ASC (10) t CAH (11) COLUMN ADDRESS t RRH (15) t CAA (20) t OAC (17) ...
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... MOSEL VITELIC Functional Description The V53C16256H is a CMOS dynamic RAM op- timized for high data bandwidth, low power applica- tions functionally similar to a traditional dynamic RAM. The V53C16256H reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS). The col- umn address “ ...
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... Refresh Interval). During Power-On, the V current requirement of CC the V53C16256H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and I current transients recommended that RAS and CAS track with V ...
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... TSOP- 0.0315 BSC [.8001 BSC] 0.039 – 0.047 [0.991 – 1.193] V53C16256H Rev. 2.3 June 1998 0.012 – 0.016 [0.305 – 0.406] 0.002 – 0.008 [0.051 – 0.203] 0.721 – 0.729 [18.31 – 18.52] ...
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... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V53C16256H GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR ...