V53C316405A Mosel Vitelic Corp, V53C316405A Datasheet

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V53C316405A

Manufacturer Part Number
V53C316405A
Description
3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM
Manufacturer
Mosel Vitelic Corp
Datasheet
MOSEL VITELIC
Features
Device Usage Chart
V53C316405A Rev. 1.2 March 1998
V53C316405A
Max. RAS Access Time, (t
Max. Column Address Access Time, (t
Min. Extended Data Out Page Mode Cycle Time, (t
Min. Read/Write Cycle Time, (t
Temperature
4M x 4-bit organization
EDO Page Mode for a sustained data rate
of 50 MHz
RAS access time: 50, 60 ns
Low power dissipation
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh and Hidden Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
Single +3.3V 0.3V Power Supply
TTL Interface
Operating
0 C to 70 C
Range
RAC
Package Outline
K
)
RC
)
V53C316405A
3.3 VOLT 4M x 4 EDO PAGE MODE
CMOS DYNAMIC RAM
CAA
)
T
PC
)
Access Time (ns)
50
1
Description
performance CMOS dynamic random access mem-
ory. The V53C316405A offers Page mode opera-
tion with Extended Data Output. The V53C316405A
has asymmetric address, 12-bit row and 10-bit col-
umn.
operation allows random access up to 1024 x 4 bits,
within a page, with cycle times as short as 20ns.
suited for a wide variety of high performance com-
puter systems and peripheral applications.
The V53C316405A is a 4,194,304 x 4 bit high-
All inputs are TTL compatible. EDO Page Mode
These features make the V53C316405A ideally
60
50 ns
25 ns
20 ns
84 ns
50
Power
Std.
Temperature
104 ns
Mark
60 ns
30 ns
25 ns
Blank
60

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V53C316405A Summary of contents

Page 1

... V53C316405A Rev. 1.2 March 1998 ) ) PC Description The V53C316405A is a 4,194,304 x 4 bit high- performance CMOS dynamic random access mem- ory. The V53C316405A offers Page mode opera- tion with Extended Data Output. The V53C316405A has asymmetric address, 12-bit row and 10-bit col- umn. ...

Page 2

... MOSEL VITELIC Pin Names A – RAS CAS WE OE I/O –I V53C316405A Rev. 1.2 March 1998 24/26-Pin Plastic SOJ/TSOP-II PIN CONFIGURATION Top View I I CAS WE RAS ...

Page 3

... A0 Buffers (10 Counter (12 A10 12 A11 Buffers (11) No. 1 Clock RAS V53C316405A Rev. 1.2 March 1998 Capacitance Symbol Parameter +0.5, 4. Address Input IN1 C RAS, CAS, WE, OE IN2 C Data Input/Output OUT *Note: Capacitance is sampled and not 100% tested. ...

Page 4

... Input High Voltage IH V TTL Output Low Voltage OL V TTL Output High Voltage OH V CMOS Output Low Voltage OL V CMOS Output High Voltage OH V53C316405A Rev. 1.2 March 1998 (1- 2ns unless otherwise specified V53C316405A Access Time Min. Typ. Max. –10 10 –10 ...

Page 5

... Output turn-off delay from OE OEZ 27 t Data to CAS low delay DZC 28 t Data to OE low delay DZO 29 t CAS high to data delay CDD high to data delay ODD V53C316405A Rev. 1.2 March 1998 = Parameter min – ...

Page 6

... CAS setup time CSR 52 t CAS hold time CHR 53 t RAS to CAS precharge time RPC 54 t Write to RAS precharge time WRP 55 t Write hold time referenced to RAS WRH V53C316405A Rev. 1.2 March 1998 = Parameter min 113 – ...

Page 7

... CPT Test Mode 60 t Write command setup time WTS 61 t Write command hold time WTH 62 t CAS hold time CHRT 63 t RAS hold time RAHT V53C316405A Rev. 1.2 March 1998 = Parameter min V53C316405A -50 -60 max. min. max. Unit Note – ...

Page 8

... I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read- write cycles. V53C316405A Rev. 1.2 March 1998 . . In case of ICC4 it can be changed once or less during ...

Page 9

... ASR V IH Row Address I/O (Inputs I/O (Outputs “H” or “L” V53C316405A Rev. 1.2 March 1998 RAS t CSH t t RCD RSH t CAS t RAD t RAL t CAH t ASC Column t t RAH RCS t CAA t OEA ...

Page 10

... V IH Row Address I/O (Inputs I/O (Outputs “H” or “L” V53C316405A Rev. 1.2 March 1998 RAS t CSH t t RCD RSH t CAS t t RAD RAL t CAH t ASC Column t CWL t RAH WCS WCH ...

Page 11

... ASR V IH Row Address I/O (Inputs I/O V (Outputs) OL “H” or “L” V53C316405A Rev. 1.2 March 1998 RAS t CSH t RCD t RSH t CAS t RAD t RAL t CAH t ASC Column t CWL t t RAH RWL OEH t ODD ...

Page 12

... V IH Address Row RAD I/O (Inputs I/O OH (Outputs “H” or “L” V53C316405A Rev. 1.2 March 1998 t RWC t RAS t CSH t t RCD RSH t CAS t CAH t ASC Column t AWD t CWD t RWD t CAA t t RCS OEA t ...

Page 13

... RAH t ASR V IH Address Row RAD I/O (Output “H” or “L” V53C316405A Rev. 1.2 March 1998 t RAS t RCD CAS CAS CAH ASC ASC CAH Column 1 Column 2 t RCS t CAC t CAA ...

Page 14

... ASR V IH Row Address Addr RAD t WCS I/O (Input “H” or “L” V53C316405A Rev. 1.2 March 1998 t RAS t RCD CAS CP CAS ASC t CAH ASC CAH Column 1 Column CWL CWL t WCS ...

Page 15

V IH RAS CSH t RCD CAS RAD t t CAH RAH t t ASR ASC V IH Address Row Column RWD t t CWD RCS V IH ...

Page 16

... MOSEL VITELIC Waveforms of RAS Only Refresh Cycle V IH RAS CAS ASR V IH Address I/O (Outputs “H” or “L” V53C316405A Rev. 1.2 March 1998 RAS t RAH Row HI-Z 16 V53C316405A CRP t RPC t ASR Row WL9 ...

Page 17

... IL t RPC CAS OEZ CDD V IH I/O (Inputs ODD V OH I/O (Outputs OFF “H” or “L” V53C316405A Rev. 1.2 March 1998 t RAS t CSR t CHR t WRP t WRH HI-Z 17 V53C316405A CRP t RPC WL10 ...

Page 18

... ASR V IH Address Row I/O (Inputs I/O (Outputs “H” or “L” V53C316405A Rev. 1.2 March 1998 RAS t RSH t RCD t t WRP ASC t t WRH CAH Column t RRH t RCS t CAA t OEA t DZC ...

Page 19

... CAS RAH t ASR V IH Address Row I/O (Input I/O (Output “H” or “L” V53C316405A Rev. 1.2 March 1998 RAS t t RCD RSH t RAD t ASC t CAH Column t WCS WRP WRH WCH ...

Page 20

... I/O OH (Outputs WRP Write Cycle I (Inputs I (Outputs V53C316405A Rev. 1.2 March 1998 t RAS CHR t CAS t RAL t t ASC CAH Column t CAA t CAC t WRH t t RCS OEA t DZC t DZO t CLZ t WCS ...

Page 21

... Address I/O (Inputs OEZ V OH I/O (Outputs “H” or “L” V53C316405A Rev. 1.2 March 1998 RAS t RPC CSR CP CHRT t t ASR RAHT Row t t WTS WTH t ODD HI-Z t CDD HI-Z t OFF 21 V53C316405A ...

Page 22

... MOSEL VITELIC Test Mode As the V53C316405A is organized internally 4-bits, a test mode cycle using 4:1 compression can be used to improve test time. Note that in the version the test time is reduced by 1/4 for a N test pattern test mode “write” the data from each I/O pin is written into four 1M blocks simultaneously (all “ ...

Page 23

... Does not include plastic or metal protrusion of 0.15 max. per side 24/26-pin 300 mil TSOP-II 0.05 [1.27] +0.005 +0.12 0.016 0.4 0.008 [0.2] –0.004 –0 0.680 0.005 [17.27 0.13] 1 Does not include plastic or metal protrusion of 0.15 max. per side V53C316405A Rev. 1.2 March 1998 0.104 0.003 [2.64 ] 0.1 0.315 min 0.148 -0.020 [0.8] min [3.75 ] -0.5 [0.003] 0.1 0.009 [0.25 ...

Page 24

... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V53C316405A GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR ...

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