V53C8125H Mosel Vitelic Corp, V53C8125H Datasheet

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V53C8125H

Manufacturer Part Number
V53C8125H
Description
ULTRA-HIGH PERFORMANCE/ 128K X 8 FAST PAGE MODE CMOS DYNAMIC RAM
Manufacturer
Mosel Vitelic Corp
Datasheet

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V53C8125H Rev. 1.7 August 1998
MOSEL VITELIC
Features
Device Usage Chart
HIGH PERFORMANCE
Max. RAS Access Time, (t
Max. Column Address Access Time, (t
Min. Fast Page Mode Cycle Time, (t
Min. Read/Write Cycle Time, (t
Temperature
128K x 8-bit organization
RAS access time: 30, 35, 40, 45, 50 ns
Fast Page Mode supports sustained data rates
up to 53 MHz
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
Refresh Interval: 256 cycles/8 ms
Available in 26/24 pin 300 mil SOJ and 28 pin
TSOP-I packages
0 C to 70 C
Operating
Range
Package Outline
.
K
RAC
)
RC
)
V53C8125H
ULTRA-HIGH PERFORMANCE,
128K X 8 FAST PAGE MODE
CMOS DYNAMIC RAM
PC
.
T
CAA
)
)
30
.
30 ns
16 ns
19 ns
30
65 ns
Access Time (ns)
35
.
1
Description
CMOS dynamic random access memory. The
V53C8125H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
columns (x9) bits within a row with cycle times as
short as 19 ns. Because of static circuitry, the CAS
clock is not in the critical timing path. The flow-
through column address latches allow address
pipelining while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8125H ideally suited for graphics,
digital signal processing and high performance pe-
ripherals.
18 ns
70 ns
35 ns
21 ns
35
40
The V53C8125H is a high speed 131,072 x 8 bit
All inputs and outputs are TTL compatible. Input
.
45
.
20 ns
40 ns
23 ns
75 ns
40
50
.
Power
Std.
.
45 ns
22 ns
25 ns
80 ns
45
PRELIMINARY
Temperature
Mark
Blank
90 ns
28 ns
24 ns
50 ns
50

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V53C8125H Summary of contents

Page 1

... Description The V53C8125H is a high speed 131,072 x 8 bit CMOS dynamic random access memory. The V53C8125H offers a combination of features: Fast Page Mode for high data bandwidth, fast usable speed, CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance ...

Page 2

... Column Address only RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable I/O - I/O Data Input, Output +5V Supply Supply Connect V53C8125H Rev. 1.7 August 1998 FAMILY DEVICE PKG K (SOJ) T (TSOP) PIN CONFIGURATION CAS 1 I/O5 2 I/O6 3 I/O7 4 I/O8 ...

Page 3

... CAS RAS RAS CLOCK GENERATOR REFRESH COUNTER ï ï ï V53C8125H Rev. 1.7 August 1998 Capacitance Symbol Parameter C Address Input IN1 C RAS, CAS, WE, OE IN2 C Data Input/Output OUT *Note: Capacitance is sampled and not 100% tested. ...

Page 4

... CC6 CC CMOS Standby V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V53C8125H Rev. 1.7 August 1998 (1- unless otherwise specified. SS V53C8125H Access Time Min. Typ. Max. Unit Ò Ò 180 35 ...

Page 5

... Write Cycle 26 t Write Command to CAS CWL Lead Time 27 t Write Command Setup Time WCS 28 t Write Command Hold Time WCH V53C8125H Rev. 1.7 August 1998 = 0V unless otherwise noted Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 30 75K 35 75K ...

Page 6

... RAS Refresh 50 t Fast Page Mode Read-Modify- PCM Write Cycle Time 51 t Transition Time (Rise and Fall Refresh Interval (512 Cycles) REF V53C8125H Rev. 1.7 August 1998 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max ...

Page 7

... Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. V53C8125H Rev. 1.7 August 1998 (max.) is measured with a maximum of two CC (min.) may undershoot to Ò ...

Page 8

... IH CAS ASR ( ADDRESS ROW ADDRESS I V53C8125H Rev. 1.7 August 1998 t RC (2) t RAS ( (23) t CSH ( RCD (6) RSH (R)(12) t CAS (5) t RAD (24 RAH (9) CAH (11) t ASC (10) COLUMN ADDRESS t CAR (44) t RCS (7) ...

Page 9

... V IH ROW ADDRESS ADDRESS RAD (24 I V53C8125H Rev. 1.7 August 1998 t RC (2) t RAS ( (23) t CSH ( RCD (6) RSH (W)(12) t CAS ( RAD (24) CAR (44 CAH (11) RAH (9) t ASC (10) COLUMN ADDRESS t CWL (26) ...

Page 10

... ADD RAD (24) t WCS (27 (32 VALID I/O DATA V53C8125H Rev. 1.7 August 1998 t RAS ( (23) t RCD (6) PC (42 (43 CAS (5) CAS (5) t CSH (4) t RAH (9) COLUMN COLUMN ADDRESS ADDRESS t RCH (14 CAH (11) ...

Page 11

... Waveforms of RAS-Only Refresh Cycle V IH RAS CRP (13 CAS ASR ( ADDRESS ROW ADDR V IL NOTE: WE Donít care V53C8125H Rev. 1.7 August 1998 t RAS (1) t CSH (4) t PCM (50 (43 CAS (5) CAS ( ASC (10) ASC (10 CAH (11) CAH (11) COLUMN ADDRESS ...

Page 12

... V IH RAS RPC (48 (43 CAS (22 I NOTE: WE, OE, A ñA = Donít care 7 0 V53C8125H Rev. 1.7 August 1998 t RAS ( CHR (49) CP (43 RCS ( (21 WCS (27) WCH (28 (33) DS (32 (2) ...

Page 13

... V IH ROW ADDRESS ADD WCS (27 (32 I V53C8125H Rev. 1.7 August 1998 RAS ( (23 RSH (R)(12) CHR (49) t RAD (24) t ASC (10) t CAH (11) COLUMN ADDRESS t RRH (15) t CAA (20) t OAC (17) ...

Page 14

... CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CAS-before-RAS refresh is activated. The V53C8125H uses the output of an internal 9-bit counter as the source of row addresses and ig- nore external address inputs. CAS-before-RAS is a ìrefresh-onlyî mode and no time has ex- data access or device selection is allowed ...

Page 15

... Refresh Interval). During Power-On, the V current requirement of CC the V53C8125H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and I current transients recommended that RAS and CAS track with V ...

Page 16

... D .007 ñ .011 .007 ñ .009 .004 ñ .008 With Plating .004 ñ .006 Base Metal Section ì D-Dî V53C8125H Rev. 1.7 August 1998 0.125 ñ 0.135 [3.175 ñ 3.429] 0.025 Min. 0.018 Typ. [0.635 Min.] [0.457 Typ.] Detail ì Aî .004 .047 .002 ñ ...

Page 17

... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V53C8125H GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR ...

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