EP2S15 ALTERA [Altera Corporation], EP2S15 Datasheet - Page 46
EP2S15
Manufacturer Part Number
EP2S15
Description
Stratix II Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP2S15.pdf
(238 pages)
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TriMatrix Memory
Figure 2–26. M-RAM Row Unit Interface to Interconnect
2–38
Stratix II Device Handbook, Volume 1
Direct Link
Interconnects
LAB
Table 2–4
the address and control signal input connections to the row unit interfaces
(L0 to L5 and R0 to R5).
C4 Interconnect
shows the input and output data signal connections along with
M-RAM Block to
LAB Row Interface
Block Interconnect Region
16
Row Interface Block
R4 and R24 Interconnects
Up to 16
Up to 28
M-RAM Block
dataout_a[ ]
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteena A [ ]
clocken_a
clock_a
aclr_a
Altera Corporation
May 2007