CY25812SCT Cypress Semiconductor, CY25812SCT Datasheet - Page 3

• Manufacturer Part Number: CY25812SCT
• Manufacturer: Cypress Semiconductor

Spread% Selection
The CY25811/12/14 SSCG products provide Center-Spread, Down-Spread and No-Spread functions. The amount of Spread% is
selected by using 3-Level. S0 and S1 digital inputs and Spread% values are given in
Table 3. Spread% Selection
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and Middle
“M”. With this 3-Level digital input logic, the 3-Level Logic is able
to detect 9 different logic states.
S0, S1 and FRSEL pins include an on chip 20K (10K/10K)
resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown below:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection).
Logic Level “1”: 3–Level logic pin connected to V
Figure 2
Figure 2. 3–Level Logic
Document Number: 38-07112 Rev. *F
(MHz)
10-12
12-14
14-16
16-20
20-24
24-28
28-32
FRSEL
S0, S1
to VSS
8-10
XIN
4-5
5-6
6-7
7-8
and
LOW (0)
LOGIC
illustrates how to implement 3–Level Logic.
FRSEL
VSS
M
M
M
M
0
0
0
0
1
1
1
1
UNCONNECTED
Center
S1 = 0
S0 = 0
MIDDLE (M)
FRSEL
S0, S1
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
(%)
and
LOGIC
S0 = M
Center
S1 = 0
± 1.2
± 1.1
± 0.9
± 0.9
± 0.9
± 0.9
± 0.9
± 0.9
±1.2
±1.1
±1.2
±1.1
(%)
HIGH (H)
FRSEL
to VDD
S0, S1
LOGIC
Center
S1 = 0
S0 = 1
DD
and
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
(%)
.
S1 = M
Center
S0 = 0
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
(%)
Modulation Rate
Spread Spectrum Clock Generators utilize frequency modulation
(FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (fmax), and minimum frequency
of the clock (fmin) determine this band of frequencies. The time
required to transition from fmin to fmax and back to fmin is the
period of the Modulation Rate. The Modulation Rate of SSCG
clocks are generally referred to in terms of frequency, or:
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider determine
the Modulation Rate.
In the case of CY25811/2/4 devices, the (Spread Spectrum)
modulation Rate, fmod, is given by the following formula:
fmod = fin/DR
where: fmod is the Modulation Rate; fin is the Input Frequency;
and DR is the Divider Ratio as given in
Frequency Range is set by FRSEL.
Table 4. Modulation Rate Divider Ratios
FRSEL
M
S1 = 1
S0 = 1
0
1
Down
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
(%)
Input Frequency Range
S1 = 1
S0 = 0
Down
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
Table
(%)
3.
16 to 32
8 to 16
(MHz)
4 to 8
S1 = M
S0 = 1
Down
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
(%)
S0 = M
S1 = 1
Down
Table
CY25811/12/14
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
(%)
4. Notice that Input
Divider Ratio
No Spread
S1 = M
S0 = M
Page 3 of 12
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512
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