MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 102

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Figure 56: Consecutive WRITE-to-WRITE
Figure 57: Nonconsecutive WRITE-to-WRITE
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
Notes:
t DQSS (NOM)
t DQSS (NOM)
DQS, DQS#
DQS, DQS#
Command
Command
1. Subsequent rising DQS signals must align to the clock within
2. DI b, etc. = data-in for column b, etc.
3. Three subsequent elements of data-in are applied in the programmed order following
4. Three subsequent elements of data-in are applied in the programmed order following
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.
1. Subsequent rising DQS signals must align to the clock within
2. DI b (or n), etc. = data-in for column b (or column n).
3. Three subsequent elements of data-in are applied in the programmed order following
4. Three subsequent elements of data-in are applied in the programmed order following
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.
Address
Address
DI b.
DI n.
DI b.
DI n.
CK#
CK#
DM
DQ
DM
DQ
CK
CK
Micron Confidential and Proprietary
WRITE
WRITE
Bank,
Bank,
Col b
Col b
T0
T0
WL ±
WL = 2
t CCD
WL = 2
NOP
NOP
T1
T1
t
DQSS
WL ± t DQSS
T1n
102
512Mb: x8, x16 Automotive DDR2 SDRAM
WRITE
NOP
Bank,
Col n
T2
DI
b
T2
DI
b
T2n
T2n
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WRITE
WL = 2
Bank,
Col n
T3
1
NOP
1
T3
T3n
T3n
WL = 2
NOP
T4
NOP
1
T4
DI
n
Transitioning Data
Transitioning Data
T4n
T4n
1
NOP
T5
DI
n
NOP
T5
1
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t
t
DQSS.
DQSS.
T5n
T5n
NOP
1
T6
Don’t Care
NOP
T6
Don’t Care
T6n
WRITE