MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 91

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MT47H32M16HR-25E AIT:G

Manufacturer Part Number
MT47H32M16HR-25E AIT:G
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
Manufacturer
Micron
Datasheet
Figure 45: Nonconsecutive READ Bursts
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
4. Three subsequent elements of data-out appear in the programmed order following
5. Shown with nominal
6. Example applies when READ commands are issued to different devices or nonconsecu-
CK#
CK#
DQ
DQ
CK
CK
DO n.
DO b.
tive READs.
READ
READ
Bank,
Bank,
Col n
Col n
T0
T0
Micron Confidential and Proprietary
NOP
NOP
T1
T1
CL = 3
t
CL = 4
AC,
NOP
NOP
T2
T2
91
t
DQSCK, and
512Mb: x8, x16 Automotive DDR2 SDRAM
READ
READ
Bank,
Bank,
Col b
Col b
T3
T3
DO
n
T3n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ.
NOP
NOP
T4
T4
DO
n
T4n
T4n
NOP
NOP
T5
T5
T5n
Transitioning Data
T6
NOP
T6
NOP
DO
b
‹ 2010 Micron Technology, Inc. All rights reserved.
T6n
T7
T7
NOP
NOP
DO
b
T7n
T7n
Don’t Care
NOP
NOP
T8
T8
READ

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