MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 76

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

CAS Latency (CL)
Figure 34: CL
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 33 (page 73). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may re-
sult.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to
nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further
detail in Posted CAS Additive Latency (AL) (page 79).
Examples of CL = 3 and CL = 4 are shown in Figure 34; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
DQS, DQS#
DQS, DQS#
Command
Command
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
Micron Confidential and Proprietary
NOP
NOP
T1
T1
CL = 3 (AL = 0)
t
AC,
76
t
DQSCK, and
512Mb: x8, x16 Automotive DDR2 SDRAM
CL = 4 (AL = 0)
NOP
NOP
T2
T2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ.
NOP
NOP
T3
T3
DO
n
t
RCD (MIN) by delaying the inter-
n + 1
DO
NOP
NOP
T4
T4
Mode Register (MR)
n + 2
DO
DO
n
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Transitioning data
n + 1
n + 3
DO
DO
NOP
NOP
T5
T5
n + 2
DO
n + 3
DO
NOP
NOP
Don’t care
T6
T6