PALCE16V8H-7SI Lattice Semiconductor Corp., PALCE16V8H-7SI Datasheet - Page 3

• Manufacturer Part Number: PALCE16V8H-7SI
• Description: Ee Cmos Zero-power 20-pin Universal Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, it is always disabled.
With the exception of MC
input signal from an adjacent I/O. MC
(CLK).
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0
conjunction with SG1, selects the configuration of the macrocell, and SL1
either active low or active high for the individual macrocell.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
MC
the adjacent pin for MC
*In macrocells MC
0
and MC
1 1
0 X
1 0
7
, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
0
and MC
7
, SG1 is replaced by SG0 on the feedback multiplexer.
7
and OE the adjacent pin for MC
0
and MC
SG1
PALCE16V8 and PALCE16V8Z Families
SL1
Figure 1. PALCE16V8 Macrocell
X
7
SL0
, a macrocell configured as a dedicated input derives the
0
X
derives its input from pin 11 (OE) and MC
x
are the control signals for all four multiplexers. In
CLK
0
through SL0
D
Q
Q
0
.
V
7
OE
CC
*SG1
and SL1
1 0
1 1
0 X
1 1
0 X
1 0
1 1
1 0
0 0
0 1
0
SL0
through SL1
x
sets the output as
X
Macrocell
Adjacent
7
x
To
, in
from pin 1
From
Adjacent
Pin
7
). SG0
16493E-2
I/O
X
3