SSTUB32872AHMLF IDT, Integrated Device Technology Inc, SSTUB32872AHMLF Datasheet
SSTUB32872AHMLF
Specifications of SSTUB32872AHMLF
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SSTUB32872AHMLF Summary of contents
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Integrated Circuit Systems, Inc. 28-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank VLP DIMMS Product Features: • 28-bit ...
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Ball Assignments 1222F—3/13/07 28 bit 1:1 Register DCKE0 D0 V QCKE0 V DD REF DCKE1 D1 GND GND Q0 D2 DODT1 ...
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General Description This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V V All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS ...
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Ball Assignment Signal Group Signal Name Ungated inputs DCKE0, DCKE1, DODT0, DODT1 Chip Select D0 ... D21 gated inputs Chip Select DCS0 , DCS1 inputs Re-driven Q0...Q21, QCS 0-1, outputs QCKE0-1, QODT0-1 Parity input PARIN Parity error PTYERR output Clock ...
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Block Diagram VREF PARIN D0 D21 DCS0 DCS1 2 DCKE0, DCKE1 DODT0, 2 DODT1 RESET CK CK 1222F—3/13/07 (CS ACTIVE) PARITY D Q GENERATOR 22 AND R CHECKER ...
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Parity Functionality Block Diagram PARIN CLOCK 1222F—3/13/ (1) This function holds the error for two D cycles. See functional description and timing diagram. 6 ICSSSTUB32872A Advance Information Qn PTYERR LATCHING AND RESET FUNCTION ...
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Register Timing RESET DCSn ACT ( PARIN PTYERR (1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a ...
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Register Timing RESET DCSn PDM , t PDMSS Qn PARIN PTYERR Unknown input e vent 1222F—3/13/ Output ...
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Register Timing RESET DCSn (1) CK ( (1) PARIN PTYERR (1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) ...
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Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...
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Electrical Characteristics - 70° 2.5 +/-0.2V SYMBOL PARAMETERS All Inputs Standby (Static) RESET = GND ...
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Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS f Clock frequency clock t Pulse duration W t Differential inputs active time ACT t Differential inputs inactive time INACT t S Setup time Hold time t ...
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CK Inputs Test Point R L Test Point VCMOS RST Inp act I DD (see 10% Note 2) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES t w Inpu t V ICR VOLTAGE ...
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LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT Output VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT Output VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 — Output Slew-Rate Measurement Information (V Notes includes probe and ...
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Test circuits and switching waveforms (cont’d) 3.3 Error output load circuit and voltage measurement information (V All input pulses are supplied by generators having the following characteristics: PRR Ω input slew rate = 1 V/ns ...
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Test circuits and switching waveforms (cont’d) 3.4 Partial-parity-out load circuit and voltage measurement information (V All input pulses are supplied by generators having the following characteristics: PRR Ω input slew rate = 1 V/ns ± ...
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A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may ...
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Revision History Rev. Issue Date Description A 5/2/2006 Initial Release. Electrical table, Ci Data input max changed from 3.5 to 5.0, CLK max B 12/12/2006 changed from 3 to 3.8 Timing table, ts Data before CK changed from 0.5 to ...