S9S12GA240F0VLL Freescale Semiconductor, S9S12GA240F0VLL Datasheet - Page 650

• Manufacturer Part Number: S9S12GA240F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 240KB FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GA240F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 240 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

Pulse-Width Modulator (S12PWM8B8CV2)
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
See
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
For boundary case programming values, please refer to
1
Read: Anytime
Write: Anytime
19.3.2.12 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
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Module Base + 0x0014 = PWMPER0, 0x0015 = PWMPER1, 0x0016 = PWMPER2, 0x0017 = PWMPER3
Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Reset
•
•
•
•
•
•
Section 19.4.2.3, “PWM Period and Duty”
W
R
The counter is written (counter resets to $00)
The channel is disabled
Left aligned output (CAEx = 0)
Center Aligned Output (CAEx = 1)
The effective period ends
The counter is written (counter resets to $00)
PWMx Period = Channel Clock Period * PWMPERx
PWMx Period = Channel Clock Period * (2 * PWMPERx)
Bit 7
1
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 19-13. PWM Channel Period Registers (PWMPERx)
1
6
6
MC9S12G Family Reference Manual,
1
5
5
for more information.
NOTE
1
4
4
Section 19.4.2.8, “PWM Boundary
1
3
3
Rev.1.23
1
2
2
Freescale Semiconductor
1
1
1
Cases”.
Bit 0
1
0