MAX1261ACEI Maxim Integrated, MAX1261ACEI Datasheet - Page 13

• Manufacturer Part Number: MAX1261ACEI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1261ACEI

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-28
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The MAX1261/MAX1263 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The parts retain
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition can
be used. At power-up, the MAX1261/MAX1263 enter
the default external clock mode.
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and bit D6 must be set to zero. The internal clock fre-
quency is then selected, resulting in a conversion time
of 3.6µs. When using the internal clock mode, tie the
CLK pin either high or low to prevent the pin from float-
ing.
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1261/MAX1263 with
clock frequencies lower than 100kHz is not recom-
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
CLK
CLK
WR
WR
with +2.5V Reference and Parallel Interface
t
CWH
______________________________________________________________________________________
ACQMOD = 0
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
ACQMOD = 0
Selecting Clock Mode
ACQUISITION STARTS
External Clock Mode
Internal Clock Mode
ACQUISITION STARTS
t
CWS
t
CH
t
CP
t
CL
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
ACQUISITION ENDS
ACQUISITION ENDS
mended, because it causes a voltage droop across the
hold capacitor in the T/H stage that results in degraded
performance.
Input (control byte) and output data are multiplexed on
a tri-state parallel interface. This parallel interface (I/O)
can easily be interfaced with standard µPs. Signals CS,
WR, and RD control the write and read operations. CS
represents the chip-select signal, which enables a µP
to address the MAX1261/MAX1263 as an I/O port.
When high, CS disables the CLK, WR, and RD inputs
and forces the interface into a high-impedance (high-Z)
state.
The control byte is latched into the device on pins
D7–D0 during a write command. Table 2 shows the
control byte format.
The output format for both the MAX1261/MAX1263 is
binary in unipolar mode and two’s complement in bipo-
lar mode. When reading the output data, CS and RD
must be low. When HBEN = 0, the lower 8 bits are read.
With HBEN = 1, the upper 4 bits are available and the
output data bits D7–D4 are set either low in unipolar
mode or set to the value of the MSB in bipolar mode
(Table 5).
CONVERSION STARTS
CONVERSION STARTS
Digital Interface
Output Format
Input Format
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