MAX1261ACEI Maxim Integrated, MAX1261ACEI Datasheet - Page 9

• Manufacturer Part Number: MAX1261ACEI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1261ACEI

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-28
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The MAX1261/MAX1263 ADCs use a successive-
approximation (SAR) conversion technique and an
input track/hold (T/H) stage to convert an analog input
signal to a 12-bit digital output. Their parallel (8 + 4)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1261/MAX1263.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH7 for the MAX1261
(Figure 3a) and to CH0–CH3 for the MAX1263 (Figure
3b), while IN- is switched to COM (Table 3).
In differential mode, IN+ and IN- are selected from ana-
log input pairs (Table 4) and are internally switched to
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1261/MAX1263
(CH7)
(CH6)
(CH5)
(CH4)
COM
CH3
CH2
CH1
CH0
CLK
WR
INT
CS
RD
with +2.5V Reference and Parallel Interface
( ) ARE FOR MAX1261 ONLY.
Pseudo-Differential Operation
_______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
CLOCK
Detailed Description
MULTIPLEXER
ANALOG
INPUT
Converter Operation
CONTROL LOGIC
Single-Ended and
LATCHES
AND
T/H
8
CHARGE REDISTRIBUTION
REF
TRI-STATE, BIDIRECTIONAL
12-BIT DAC
I/O INTERFACE
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
the end of the acquisition interval, the T/H switch
opens, retaining charge on C
signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node 0 to 0V within the
limits of 12-bit resolution. This action is equivalent to
transferring a 12pF[(V
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
4
APPROXIMATION
4
SUCCESSIVE-
8-BIT DATA BUS
REGISTER
MUX
12
D0–D7
8
A
8
2.05
8
V
=
HOLD
REFADJ
from the positive input (IN+) to the
COMP
IN+
17kΩ
MAX1261
MAX1263
) - (V
HOLD
REFERENCE
IN-
1.22V
)] charge from C
as a sample of the
HBEN
V
V
GND
DD
LOGIC
HOLD
HOLD
. At
9