MAX1281BEUP-T Maxim Integrated, MAX1281BEUP-T Datasheet - Page 16

• Manufacturer Part Number: MAX1281BEUP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1281BEUP-T

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 559 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

progress. In software power-down mode, the serial
interface remains active, waiting for a new control byte
to start conversion and switch to full-power mode.
Once the conversion is completed, the device goes
into the programmed power mode until a new control
byte is written.
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). During
power-on reset, when exiting software full power-down
mode or exiting hardware shutdown, the device goes
immediately into full-power mode and is ready to con-
vert after 2µs when using an external reference. When
using the internal reference, wait for the typical power-
Serial 12-Bit ADCs with Internal Reference
Figure 8. Continuous 16-Clock/Conversion Timing
Table 4. Software-Controlled Power Modes
*Circuit operation between conversions; during conversion, all circuits are fully powered up.
16
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
PD1/PD0
______________________________________________________________________________________
00
01
10
11
SSTRB
DOUT
SCLK
DIN
CS
HIGH-Z
HIGH-Z
S
1
Full Power-Down
(FULLPD)
Fast Power-Down
(FASTPD)
Reduced-Power
Mode (REDPD)
Operating Mode
CONTROL BYTE 0
MODE
8
B11
12
CONVERTING
CONVERSION RESULT 0
TOTAL SUPPLY CURRENT
2.5mA
2.5mA
2.5mA
2.5mA
16
S
B6
1
CONTROL BYTE 1
5
B0
CONVERSION
8
AFTER
0.9mA
1.3mA
2.0mA
2µA
up delay from a full power-down (software or hard-
ware), as shown in Figure 9.
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software shutdown is
asserted, the ADC completes the conversion in
progress and powers down into the specified low-
quiescent-current state (2µA, 0.9mA, or 1.3mA).
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1280/MAX1281 into their full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 =
1, a 0.9mA power-down starts after the conversion.
B11
12
CONVERSION RESULT 1
16
S
B6
1
INPUT COMPARATOR
CONTROL BYTE 2
Reduced Power
Reduced Power
5
Full Power
B0
Off
8
CIRCUIT SECTIONS*
B11
12
Software Power-Down
16
S
B6
1
REFERENCE
ETC
Off
On
On
On
5