MAX1281BEUP-T Maxim Integrated, MAX1281BEUP-T Datasheet - Page 22

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MAX1281BEUP-T

Manufacturer Part Number
MAX1281BEUP-T
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1281BEUP-T

Number Of Channels
8/4
Architecture
SAR
Conversion Rate
300 KSPs
Resolution
12 bit
Input Type
Single-Ended/Pseudo-Differential
Snr
70 dB
Interface Type
4-Wire (SPI, Microwire, QSPI, TMS320)
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-20
Maximum Power Dissipation
559 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
2.5 V
Serial 12-Bit ADCs with Internal Reference
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
V5 are the amplitudes of the 2nd- through 5th-order har-
monics, respectively.
Figure 19. MAX1280/MAX1281-to-TMS320 Serial Interface
22
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
SSTRB
DOUT
SCLK
DIN
______________________________________________________________________________________
CS
THD
1
=
is the fundamental amplitude, and V
20
START
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
×
log
SEL2
Effective Number of Bits
V
SEL1
2
2
+
V
3
SEL0
2
+
V
V
UNI/BIP SGI/DIF
4
1
2
+
V
4
2
+
V
2
5
through
PD1
2
PD0
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
ANALOG
INPUTS
0.01µF
+2.5V
4.7µF
0 TO
MSB
Typical Operating Circuit
CH0
CH8
REF
REFADJ
MAX1280
MAX1281
Spurious-Free Dynamic Range
B10
SSTRB
DOUT
SHDN
SCLK
V
V
COM
GND
DD1
DD2
DIN
CS
B1
B0
+5V OR
+3V
0.1µF
I/O
SCK (SK)
MISO (SI)
V
MOSI (SO)
DD
HIGH IMPEDANCE
HIGH IMPEDANCE
CPU
V
SS

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