MAX1064ACEG Maxim Integrated, MAX1064ACEG Datasheet - Page 10

• Manufacturer Part Number: MAX1064ACEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1064ACEG

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 61 dB
• Interface Type: Serial
• Operating Supply Voltage: 2.7 V to 5.5 V, 5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Figure 3a. MAX1060 Simplified Input Structure
Internal protection diodes, which clamp the analog
input to V
swing within (GND - 300mV) to (V
damage. However, for accurate conversions near full
scale, neither input should exceed (V
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
The MAX1060/MAX1064 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part enters
its hold mode on the fourth falling edge of the clock after
writing the control byte. Note that, in internal clock mode,
this is approximately 1µs after writing the control byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive (+) input. In
pseudo-differential operation, IN- connects to the nega-
tive input (-) and the difference of
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and C
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
10
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS CH0/CH1,
COM
______________________________________________________________________________________
CH0
CH1
CH2
CH3
CH4
CH6
CH5
CH7
REF
DD
INPUT
MUX
and GND, allow each input channel to
10-BIT CAPACITIVE DAC
C
SWITCH
–
12pF
C
HOLD
TRACK
SWITCH
CH2/CH3, CH4/CH5, AND CH6/CH7
+
Analog Input Protection
T/H
R
800Ω
IN
HOLD
ZERO
DD
|
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
(IN+) - (IN-)
COMPARATOR
DD
+ 300mV) without
+ 50mV) or be
Track/Hold
|
is sam-
HOLD
t
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
where R
R
the input capacitance of the ADC. Source impedances
below 3kΩ have no significant impact on the MAX1060/
MAX1064s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Along with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
The MAX1060/MAX1064 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth. These fea-
tures make it possible to digitize high-speed transients
and measure periodic signals with bandwidths exceed-
ing the ADC’s sampling rate by using undersampling
techniques. To avoid aliasing high-frequency signals
into the frequency band of interest, anti-alias filtering is
recommended.
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1060/MAX1064 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
conversion. The sampling interval occurs at the end of
Figure 3b. MAX1064 Simplified Input Structure
ACQ
IN
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS CH0/CH1
COM
(800Ω) is the input resistance, and C
CH0
CH1
CH2
CH3
, is the maximum time the device takes to acquire
S
REF
is the source impedance of the input signal,
INPUT
MUX
10-BIT CAPACITIVE DAC
t
C
ACQ
SWITCH
–
C
12pF
HOLD
TRACK
= 7(R
SWITCH
+
AND CH2/CH3
T/H
R
800Ω
S
Starting a Conversion
IN
HOLD
+ R
ZERO
IN
Input Bandwidth
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
)C
COMPARATOR
IN
IN
(12pF) is