MAX1064ACEG Maxim Integrated, MAX1064ACEG Datasheet - Page 13

• Manufacturer Part Number: MAX1064ACEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1064ACEG

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 61 dB
• Interface Type: Serial
• Operating Supply Voltage: 2.7 V to 5.5 V, 5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1 and
bit D6 must be set to zero. The internal clock frequency
is then selected, resulting in a 3.6µs conversion time.
When using the internal clock mode, connect the CLK
pin either high or low to prevent the pin from floating.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
CLK
CLK
WR
WR
CLK
CLK
WR
WR
with +2.5V Reference and Parallel Interface
t
CWH
ACQMOD = 1
ACQMOD = 1
______________________________________________________________________________________
ACQMOD = 0
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
ACQMOD = 0
ACQUISITION STARTS
ACQUISITION STARTS
ACQUISITION STARTS
t
t
DH
DH
Internal Clock Mode
ACQUISITION STARTS
t
CWS
t
CH
t
CP
t
CL
WR GOES HIGH WHEN CLK IS HIGH.
WR GOES HIGH WHEN CLK IS LOW.
WR GOES HIGH WHEN CLK IS LOW.
WR GOES HIGH WHEN CLK IS HIGH.
ACQUISITION ENDS
ACQUISITION ENDS
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. Proper operation requires a 100kHz to
7.6MHz clock frequency with 30% to 70% duty cycle.
Operating the MAX1060/MAX1064 with clock frequen-
cies lower than 100kHz is not recommended, because
it causes a voltage droop across the hold capacitor in
the T/H stage that results in degraded performance.
ACQUISITION ENDS
CONVERSION STARTS
t
CONVERSION STARTS
ACQUISITION ENDS
CWH
ACQMOD = "0"
ACQMOD = "0"
t
CWS
External Clock Mode
CONVERSION STARTS
CONVERSION STARTS
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