MAX1064ACEG Maxim Integrated, MAX1064ACEG Datasheet - Page 9

• Manufacturer Part Number: MAX1064ACEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1064ACEG

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 61 dB
• Interface Type: Serial
• Operating Supply Voltage: 2.7 V to 5.5 V, 5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The MAX1060/MAX1064 ADCs use a successive-
approximation (SAR) conversion technique and an
input track-and-hold (T/H) stage to convert an analog
input signal to a 10-bit digital output. Their parallel (8 + 2)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1060/MAX1064.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuits in
Figures 3a and 3b. In single-ended mode, IN+ is inter-
nally switched to channels CH0–CH7 for the MAX1060
(Figure 3a) and to CH0–CH3 for the MAX1064 (Figure
3b), while IN- is switched to COM (Table 3). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 4).
Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1060/MAX1064
(CH7)
(CH6)
(CH5)
(CH4)
COM
CH3
CH2
CH1
CH0
CLK
WR
INT
CS
RD
with +2.5V Reference and Parallel Interface
( ) ARE FOR MAX1060 ONLY.
Pseudo-Differential Operation
_______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
CLOCK
MULTIPLEXER
Detailed Description
ANALOG
INPUT
Converter Operation
CONTROL LOGIC
Single-Ended and
LATCHES
AND
T/H
8
CHARGE REDISTRIBUTION
REF
TRI-STATE, BIDIRECTIONAL
10-BIT DAC
I/O INTERFACE
In differential mode, IN- and IN+ are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
the end of the acquisition interval, the T/H switch
opens, retaining the charge on C
the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node zero to 0V within
the limits of 10-bit resolution. This action is equivalent to
transferring a 12pF [(V
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
APPROXIMATION
2
2
SUCCESSIVE-
8-BIT DATA BUS
REGISTER
MUX
D0–D7
10
8
A
8
2.05
8
V
=
HOLD
REFADJ
from the positive input (IN+) to the
IN+
COMP
17kΩ
MAX1060
MAX1064
) - (V
IN-
REFERENCE
)] charge from C
1.22V
HOLD
as a sample of
HOLD
HBEN
V
V
GND
DD
LOGIC
HOLD
. At
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