MAX1064ACEG Maxim Integrated, MAX1064ACEG Datasheet - Page 16

• Manufacturer Part Number: MAX1064ACEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1064ACEG

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 61 dB
• Interface Type: Serial
• Operating Supply Voltage: 2.7 V to 5.5 V, 5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

only 50µs are required after power-up. Enter standby
mode by performing a dummy conversion with the con-
trol byte specifying standby mode.
Note: Bypass capacitors larger than 4.7µF between
REF and GND result in longer power-up delays.
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Figure 8 depicts the nominal, unipolar input/output (I/O)
transfer function, and Figure 9 shows the bipolar I/O
transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary, with 1 LSB = V
When running at the maximum clock frequency of
7.6MHz, the specified 400ksps throughput is achieved
by completing a conversion every 19 clock cycles: 1
write cycle, 3 acquisition cycles, 13 conversion cycles,
and 2 read cycles. This assumes that the results of the
last conversion are read before the next control byte is
written. It is possible to achieve higher throughputs
(Figure 10), up to 475ksps, by first writing a control
word to begin the acquisition cycle of the next conver-
sion, then reading the results of the previous conver-
sion from the bus. This technique allows a conversion
to be completed every 16 clock cycles. Note that
switching the data bus during acquisition or conversion
can cause additional supply noise that can make it diffi-
cult to achieve true 10-bit performance.
For best performance, use printed circuit boards. Wire-
wrap configurations are not recommended since the lay-
out should ensure proper separation of analog and digital
traces. Do not run analog and digital lines parallel to each
other, and do not lay out digital signal paths underneath
the ADC package. Use separate analog and digital PC
board ground sections with only one star point (Figure
11) connecting the two ground systems (analog and digi-
tal). For lowest noise operation, ensure the ground return
to the star ground’s power supply is low impedance and
as short as possible. Route digital signals far away from
sensitive analog and reference inputs.
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 6. Full Scale and Zero Scale for Unipolar and Bipolar Operation
16
______________________________________________________________________________________
Zero scale
Full scale
Layout, Grounding, and Bypassing
—
UNIPOLAR MODE
Maximum Sampling Rate/
REF
/ 1024.
Achieving 475ksps
Transfer Function
V
REF
COM
—
+ COM
Figure 8. Unipolar Transfer Function
Figure 9. Bipolar Transfer Function
*COM
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
Negative full scale
111 . . . 111
111 . . . 110
100 . . . 010
100 . . . 001
100 . . . 000
011 . . . 111
011 . . . 110
000 . . . 000
Positive full scale
011 . . . 101
000 . . . 001
≤
OUTPUT CODE
V
Zero scale
REF
OUTPUT CODE
/ 2
(COM)
0
- FS
1 LSB =
FS = REF
ZS = COM
-FS =
1 LSB =
FS = REF + COM
ZS = COM
1
-REF
2
1024
2
REF
BIPOLAR MODE
2
1024
REF
+ COM
+ COM
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
COM*
512
-V
V
REF
REF
FULL-SCALE
TRANSITION
COM
/2 + COM
/2 + COM
FS -
+FS - 1 LSB
3
/
2
LSB
FS