S9S12G128F0VLLR Freescale Semiconductor, S9S12G128F0VLLR Datasheet - Page 709

• Manufacturer Part Number: S9S12G128F0VLLR
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLLR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

1
Freescale Semiconductor
MODFEN
n is used later in this document as a placeholder for the selected transfer width.
BIDIROE
SPISWAI
XFRW
SPC0
Field
6
4
3
1
0
Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL
becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and
SPIDRL form a 16-bit data register. Please refer to
information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a
change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 8-bit Transfer Width (n = 8)
1 16-bit Transfer Width (n = 16)
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode.
1 Stop SPI clock generation when in wait mode.
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
Bidirectional
Bidirectional
Pin Mode
Normal
Normal
SPC0
0
1
0
1
Table
Table 21-4. Bidirectional Pin Configurations
MC9S12G Family Reference Manual, Rev.1.23
Table 21-3. SPICR2 Field Descriptions
BIDIROE
21-2. In master mode, a change of this bit will abort a transmission in progress and
1
X
X
0
1
0
1
1
Master Mode of Operation
Slave Mode of Operation
MISO not used by SPI
Slave Out
Master In
Slave I/O
Description
Slave In
MISO
Section 21.3.2.4, “SPI Status Register (SPISR)
MOSI not used by SPI
Serial Peripheral Interface (S12SPIV5)
Master Out
Master I/O
Master In
Slave In
MOSI
Table
21-4. In master
for
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