S9S12GA240F0MLF Freescale Semiconductor, S9S12GA240F0MLF Datasheet - Page 376

• Manufacturer Part Number: S9S12GA240F0MLF
• Description: 16-bit Microcontrollers - MCU 16BIT 240KB FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GA240F0MLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 240 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.6
This register controls S12CPMU clock selection.
Read: Anytime
Write:
378
0x0039
Reset
1. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
2. All bits in Special Mode (if PROT=0).
3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
4. COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
5. COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once is taken.
W
R
PLLSEL
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1
or insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with
COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for
other clock domains: for instance core clock etc.).
S12CPMU Clock Select Register (CPMUCLKS)
1
7
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful.
= Unimplemented or Reserved
Figure 10-9. S12CPMU Clock Select Register (CPMUCLKS)
PSTP
0
6
MC9S12G Family Reference Manual,
0
0
5
OSCSEL1
COP
NOTE
0
4
PRE
0
3
Rev.1.23
PCE
0
2
OSCSEL
Freescale Semiconductor
RTI
0
1
OSCSEL0
COP
0
0