MM912H634DV1AER2 Freescale Semiconductor, MM912H634DV1AER2 Datasheet
MM912H634DV1AER2
Specifications of MM912H634DV1AER2
Available stocks
Related parts for MM912H634DV1AER2
MM912H634DV1AER2 Summary of contents
Page 1
... This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010-2012. All rights reserved.. All rights reserved. • Low Power Modes with cyclic sense & forced wake-up • Current Sense Module with selectable gain • ...
Page 2
... The device part number is following the standard scheme below Product Category Memory Type MCU Core MM – Qualified Standard 9 – FLASH, OTP 08 – HC08 SM – Custom Device Blank - ROM 12 – HC12 PM – Prototype Device Freescale Semiconductor Max. Bus Package Frequency (MHz BUSMAX 98ASA00173D 20 48-PIN LQFP-EP 98ASH00962A 16 48-PIN LQFP (3) ...
Page 3
... External Oscillator (S12SS12SCRGV1 256 4.34 Real Time Interrupt (S12SRTIV1 258 4.35 Computer Operating Properly (S12SCOPV1 263 4.36 32 kbyte Flash Module (S12SFTSR32KV1 269 4.37 Die-to-Die Initiator (D2DIV1 300 4.38 Serial Peripheral Interface (S12SPIV4 312 5 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 5.1 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 6 Revision History 337 Freescale Semiconductor Table of Contents MM912F634 3 ...
Page 4
... Ordering Information EVSS EVDD VDD VDDX DGND VSENSE VS1 VS2 HS1 HS2 HSUP LIN Freescale Semiconductor PTA DDRA Internal Bus Figure 3. Device Block Diagram BKGD/MODC RESET RESET_A TCLK TEST_A Internal Bus ISENSEH ISENSEL LS2 PGND LS1 MM912F634 4 ...
Page 5
... PA1 10 PA0 11 EVSSX 12 EVDDX The device exposed pad (package option AE only) is recommended to be connected to GND. Not all pins are available for analog die option 2. See for details. Freescale Semiconductor Figure 4. MM912F634 Pin Out NOTE Section 4.2.3, “Analog Die Options" ...
Page 6
... DGND Digital Ground Pin 18 VSENSE Voltage Sense Pin Freescale Semiconductor Description This pin is reserved for alternative function and should be left floating or connected to GND. EXTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock. See Section 4.33, “ ...
Page 7
... ADC Reference Voltage 30 AGND Analog Ground Pin Freescale Semiconductor Description This pin is the device power supply pin 1. VS1 is primarily supplying the VDDX Voltage regulator and the Hall Sensor Supply Regulator (HSUP). VS1 can be sensed via a voltage divider through the AD converter. Reverse battery protection diode is required. See Section 4.4, “ ...
Page 8
... High Voltage Input 5 37 LS1 Low Side Output 1 38 PGND Power Ground Pin Freescale Semiconductor Description This pins is the High Voltage Input 0 with the following shared functions: • Digital High Voltage Input 0. When used as digital input, a series resistor (R ) must be used to protect against automotive transients. Lx • ...
Page 9
... An optional filter capacitor C is recommended to be placed between the board connector and R Lx performance. Freescale Semiconductor Low Side output 2 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. ...
Page 10
... Function 2 EXTAL — XTAL — RESET — TEST — BKGD MODC PA5 — PA4 — PA3 SS PA2 SCK PA1 MOSI PA0 MISO Freescale Semiconductor Internal Pull Resistor Power Supply CTRL Pull-up DDX N.A. RESET pin V Always on DDX V NA DDX ...
Page 11
... HSUP Pin Voltage (DC) VSENSE Pin Voltage (DC) Note: 6. Caution: As this pin is adjacent to the VDDX pin, care should be taken to avoid a short between VDD and VDDX, for example, during the soldering process. A short-circuit between these pins might lead to permanent damage. Freescale Semiconductor Symbol Value -0 -0 ...
Page 12
... MCU Bus frequency Operating Ambient Temperature MM912x634xVxxx Operating Junction Temperature - Analog Die Operating Junction Temperature - MCU Die Note: 9. During power up and power down sequence always V 10. f frequency ratings differ by device and is specified in BUSMAX Freescale Semiconductor Symbol V EDDX V EDD ILV V TEST ...
Page 13
... VDD and VDDX. STOP_M 14. I denotes the sum of the currents flowing into VDD and VDDX. WAIT_M 15. f frequency ratings differ by device and is specified in BUSMAX Freescale Semiconductor Symbol I RUN_A 5.5 V, -40 °C VDDX = 2. 5 ...
Page 14
... Watchdog Enable Voltage (fixed voltage) Table 13. Static Electrical Characteristics - Voltage Regulator 5V (VDDX) Ratings Normal Mode Output Voltage 1.0 mA < < 80 mA; 5.5 V < V VDDX VDDXINTERNAL Normal Mode Output Current Limitation (I Freescale Semiconductor = 25 °C under nominal conditions unless otherwise noted. A Symbol V POR V LVI V LVI_H ...
Page 15
... LOAD SUP T 150 ° mA; 3 LOAD SUP Output Voltage: ( SUP Load Regulation (1.0 mA < I < 30 mA; V HSUP Freescale Semiconductor Symbol V DDXSTOP 25 ° < VDDX VDDXINTERNAL ) I VDDXLIMSTOP LR XRUN LR XSTOP LD XRUN < XCRK LD ...
Page 16
... Input Leakage Current; VBAT disconnected; VSUP_DEVICE = GND; 0 < VBUS < Receiver Input Voltage; Receiver Dominant State Receiver Input Voltage; Receiver Recessive State Receiver Threshold Center ( TH_DOM Receiver Threshold Hysteresis (V TH_REC Voltage Drop at the serial Diode Freescale Semiconductor Symbol C HSUP C HSUP_R Symbol R DS(ON) < 9 ...
Page 17
... LIN Pull-up Resistor Bus Wake-up Threshold from Stop or Sleep Bus Dominant Voltage Note: 19. Considering drop from VBAT to LIN, at very low VBAT level, the internal logic will detect a dominant as the threshold will not decrease with VSUP. Freescale Semiconductor Symbol R SLAVE (19) V WUP ...
Page 18
... Input voltage > Input capacitance Clamp Voltage when selected as analog input Analog Input impedance = 10 kOhm max, Capacitance = 12 pF Analog Input Capacitance = 12 pF Maximum current all PTB combined (VDDX capability) Output Drive strength at 10 MHz Freescale Semiconductor Symbol V THL V THH V HYS ...
Page 19
... CSGS (Current Sense Gain Select) = 110 CSGS (Current Sense Gain Select) = 111 Gain Accuracy Offset (23) Resolution ISENSEH, ISENSEL Input Common Mode Voltage Range Current Sense Module - Normal Mode Current Consumption Adder (CSE = 1) Note: 23. RES = 2.44 mV/(GAIN*R ) SHUNT Freescale Semiconductor Static Electrical Characteristics (21) Symbol Min Typ V ADC2p5RUN 2,45 2 ...
Page 20
... VS1SENSE Input Divider Ratio (RATIO VS1SENSE 5.5 V < V < SUP VS1SENSE error - whole path (VS1 pin to Digital value) VSENSE Series Resistor (25) VSENSE Capacitor (optional) Note: 25. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" Freescale Semiconductor Symbol TS G (24) TS Err (24) T 0.15V (24) T 1.984V ...
Page 21
... IH IL Internal pull-down resistance (V min > input voltage > V max Input capacitance (26) Injection current Single pin limit Total device Limit, sum of all injected currents Note: 26. Refer to Section 3.8, “ESD Protection and Latch-up Freescale Semiconductor Symbol Min V 0.65 0 ...
Page 22
... Cyclic Sense / Forced Wake-up Timing Accuracy - trimmed Time between HSx on and Lx sense during cyclic sense HSx ON duration during Cyclic Sense HSx ON duration during Cyclic Sense - trimmed Note: 29. Trimming parameters are not available in Sleep mode. Freescale Semiconductor = 25 °C under nominal conditions unless otherwise noted. A Symbol t VTO f ...
Page 23
... BUS_REC(MIN) BIT Duty Cycle 0.389 x V REC(MIN) SUP TH = 0.251 x V DOM(MIN) SUP 7.6 V V µs SUP BIT = /( BUS_REC(MAX) BIT Freescale Semiconductor Symbol t IWDTO WD WD ACT Symbol f HS Symbol f LS Symbol t PROPWL BR FAST (31) MAX ( ...
Page 24
... LIN signal threshold defined at each parameter. See 32. LIN Transmitter Timing, (V from 7 See SUP VSU TXD RXD Figure 6. LIN Timing Measurements for Normal Baud Rate Freescale Semiconductor Symbol t TRAN_SYM 40%) 1 1.0 k, 6 660 500 . Measurement thresholds: 50% of TXD and C BUS Figure 5 ...
Page 25
... Electrical Characteristics Figure 7. LIN Timing Measurements for Slow Baud Rate TX BUS ttran_pdf60% ttran_pdf40% Freescale Semiconductor Figure 8. LIN Receiver Timing ttran_pdr40% ttran_pdr60% Figure 9. LIN Transmitter Timing Dynamic Electrical Characteristics 60% 40% MM912F634 25 ...
Page 26
... The minimum program and erase times shown in maximum times are calculated for minimum f 3.6.2.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency f and can be calculated according to the following formula. Freescale Semiconductor Symbol f PTB t PDR ...
Page 27
... The given erase time (t consecutive pulses. Erasing a 512-byte Flash sector takes: The setup time can be ignored for this operation. 3.6.2.1.4 Mass Erase Erasing a NVM block takes: The setup time can be ignored for this operation. Freescale Semiconductor 1 1 ------------------------ - ---------- - t ...
Page 28
... ERA 38. Minimum erase times are achieved under maximum NVM operating frequency, f 39. Minimum time, if first word in the array is not blank. 40. Maximum time to complete check on an erased block. Freescale Semiconductor t ª location Þ Þ ...
Page 29
... Figure 10. For additional information on how Freescale defines Typical Endurance, refer to Engineering Bulletin EB619. 300 250 200 150 100 50 0 -40 -20 Figure 10. Typical Flash Cycling Endurance vs. Temperature Freescale Semiconductor Symbol , (41) (42) 85 C t JAVG FLRET , (41) (42) 85 C ...
Page 30
... Reset input pulse width, minimum input time Startup from Reset Note: 45. Reference Frequency is factory trimmed 46. % deviation from target frequency, target frequency MHz kHz, MULT = $7D DCO = IREF_TRIM = Freescale Semiconductor Symbol 105 IREF_TRIM 140 IREF_TRIM f FLLREF f ...
Page 31
... V V PORD V PORA POR Table 40. Power On Reset Characteristics Rating Power On Reset assert level Power On Reset de-assert level Freescale Semiconductor are derived from the VDD supply. After releasing the POR reset, the oscillator PORA V Figure 11. Power on Reset Symbol Min V 0.84 PORA V PORD ...
Page 32
... This section provides electrical parameters and ratings for the SPI. Table 42. Measurement Conditions Description Drive mode (49) Load capacitance C on all outputs LOAD , Thresholds for delay measurement points Note: 49. Timing specified for equal load on all SPI output pins. Avoid asymmetric load. Freescale Semiconductor Dynamic Electrical Characteristics CMFA. Symbol Min Typ f 4.0 - OSC t - 2.0 ...
Page 33
... MISO MSB IN2 (Input) 9 MOSI Port Data Master MSB OUT2 (Output) 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB. Freescale Semiconductor Bit MSB-1… Bit MSB-1…1 Figure 12. SPI Master Timing (CPHA = ...
Page 34
... Data setup time (inputs) Data hold time (inputs) Data valid after SCK edge Data valid after SS fall (CPHA = 0) Data hold time (outputs) Rise and fall time inputs Rise and fall time outputs Freescale Semiconductor Dynamic Electrical Characteristics Symbol Min Typ f 1/2048 ...
Page 35
... SCK (CPOL = 1) (Input) 9 MISO See Slave Note (Output MOSI MSB IN (Input) NOTE: Not defined Freescale Semiconductor Bit MSB-1…1 6 Bit MSB-1…1 Figure 14. SPI Slave Timing (CPHA = Bit MSB-1…1 MSB OUT 6 Bit MSB-1…1 Figure 15 ...
Page 36
... Slave MISO disable time Data valid after SCK edge Data valid after SS fall Data hold time (outputs) Rise and fall time inputs Rise and fall time outputs Note: 50. 0.5 t added due to internal synchronization delay BUS Freescale Semiconductor Symbol Min Typ SCK t 4.0 - ...
Page 37
... HS Over-temperature Shutdown Hysteresis (51) LS Over-temperature Shutdown LS Over-temperature Shutdown Hysteresis (51) LIN Over-temperature Shutdown LIN Over-temperature Shutdown Hysteresis Note: 51. Guaranteed by characterization. Functionality tested. Freescale Semiconductor 105 °C, unless otherwise noted. Typical values noted °C under nominal conditions unless otherwise noted. A Symbol (51) T HTI T ...
Page 38
... Note: 52. Input Voltage Limit = -2.5 to 7.5 V. 53. With C (10…100 nF) as part of the battery path. VBAT 54. Certification available on request 55. Tested internally only; certification pending Freescale Semiconductor Symbol (54) , unpowered, contact (55) , unpowered, contact , unpowered, contact discharge, , powered, contact discharge, ESD Protection and Latch-up Immunity ...
Page 39
... For immunity against transients for the LIN, Lx, and VBAT is specified according to the LIN Conformance Test Specification - Section LIN EMC Test Specification refer to the LIN Conformance Test Certification Report - available as a separate document from ISO. Freescale Semiconductor Additional Test Information ISO7637-2 MM912F634 ...
Page 40
... Freescale Semiconductor Trimming". Section 4.38, “Serial Peripheral Interface NOTE Table 47 is not allocated to any module. This register Module PIM (port integration module) Reserved Part ID register ...
Page 41
... R 0 0x0018-0 Reserved x0019 W R 0x001A PARTIDH W R 0x001B PARTIDL 0x001C- Reserved 0x001E W Table 50. 0x001F Interrupt Module (S12SINT) R 0x001F IVBR W Freescale Semiconductor Bit 6 Bit 5 Bit 4 0 PTA5 PTA4 DDRA5 DDRA4 DDRA3 PTD6 PTD5 PTD4 ...
Page 42
... This represents the contents if the Comparator A control register is blended into this address. 58. This represents the contents if the Comparator B control register is blended into this address. 59. This represents the contents if the Comparator C control register is blended into this address. Freescale Semiconductor Bit 6 Bit 5 Bit 4 0 ...
Page 43
... W R 0x003D RTICNT RTICNT7 W Table 55. 0x003E–0x003F Computer Operating Properly (COP) Address Name Bit 7 R 0x003E COPCTL WCOP 0x003F ARMCOP W Bit 7 Freescale Semiconductor Bit 6 Bit 5 Bit DP14 DP13 DP12 Bit 6 Bit 5 Bit 4 RDIV[2:0] BDIV[3:0] MULT[6:0] ...
Page 44
... Bit 7 R 0x00E8 SPI0CR1 SPIE 0x00E9 SPI0CR2 0x00EA SPI0BR W R SPIF 0x00EB SPI0SR 0x00EC Reserved W Freescale Semiconductor Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 0 D2DCW D2DSWAI ACKERF CNCLF TIMEF D2DBSY 0 0 SZ8 0 NBLK ADR[7:0] DATA[15:8] ...
Page 45
... FADDRHI 0x0109 FADDRLO W FAB7 R 0x010A FDATAHI FD15 W R 0x010B FDATALO FD7 0x010C FRSV2 0x010D FRSV3 W Freescale Semiconductor Bit 6 Bit 5 Bit 4 Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 PRDIV8 FDIV5 FDIV4 KEYEN0 0 0 ...
Page 46
... D2D Non Blocking Access (D2DI Offset Name ISR (hi) 0x00 Interrupt Source Register ISR (lo) 0x01 Interrupt Source Register IVR 0x02 Interrupt Vector Register VCR 0x04 Voltage Control Register Freescale Semiconductor Bit 6 Bit 5 Bit Bit 6 Bit 5 ...
Page 47
... High Side Control Register HSSR 0x29 High Side Status Register LSCR 0x30 Low Side Control Register LSSR 0x31 Low Side Status Register LSCEN 0x32 Low-Side Control Enable Register HSR 0x38 Hall Supply Register Freescale Semiconductor VROVC ...
Page 48
... PWM Ch Period Register 0 PWMPER1 0x67 PWM Ch Period Register 1 PWMDTY0 0x68 PWM Ch Duty Register 0 PWMDTY1 0x69 PWM Ch Duty Register 1 ACR 0x80 ADC Config Register ASR 0x81 ADC Status Register Freescale Semiconductor CSE LBKDIE RXEDGIE SBR12 W R SBR7 ...
Page 49
... ADR6 (hi) 0x92 ADC Data Result Register 6 ADR6 (lo) 0x93 ADC Data Result Register 6 ADR7 (hi) 0x94 ADC Data Result Register 7 ADR7 (lo) 0x95 ADC Data Result Register 7 ADR8 (hi) 0x96 ADC Data Result Register 8 Freescale Semiconductor CH15 CH14 W R CH7 CH6 CH5 W R CC15 ...
Page 50
... OC3D 0xC3 Output Comp 3 Data Reg TCNT (hi) 0xC4 Timer Count Register TCNT (lo) 0xC5 Timer Count Register TSCR1 0xC6 Timer System Control Reg 1 TTOV 0xC7 Timer Toggle Overflow Reg Freescale Semiconductor adr8 1 adr8 adr9 9 adr9 8 adr9 7 adr9 ...
Page 51
... Trimming Reg 0 CTR1 0xF1 Trimming Reg 1 CTR2 0xF2 Trimming Reg 2 CTR3 0xF3 Trimming Reg 3 SRR 0xF4 Silicon Revision Register Note: 60. Registers not shown are reserved and must not be accessed. Freescale Semiconductor OM3 OL3 OM2 W R EDG3B EDG3A EDG2B EDG2A W R ...
Page 52
... Beyond this chapter, there will be no additional note or differentiation between the different implementations. The following section describes the differences between analog die options 1 and 2. Table 68. Analog Die Options (continued) Feature Current Sense Module Wake Up Inputs (Lx) Freescale Semiconductor NOTE - Mask set errata document for details on the analog die ...
Page 53
... ADC Conv Complete Reg The ADC Data Result Reg 9 must be ignored. ADR9 (hi) 0x98 ADC Data Result Register 9 ADR9 (lo) 0x99 ADC Data Result Register 9 Freescale Semiconductor New PIN name NC ISENSE feature not bonded and/or not tested. Connect PINs 40 and 41 (NC) to GND ...
Page 54
... ADC Conversion Ctrl Reg ACCR (lo) 0x83 ADC Conversion Ctrl Reg Freescale Semiconductor One or more Lx wake up inputs are not available based on the analog die option. Not available Lx inputs are not bonded and/or not tested. Connect not available Lx pins (NC) to GND. R required on those pins. ...
Page 55
... ADRx (lo) ADC Data Result Register x 4.2.3.2.3 Functional Considerations For the not available Lx inputs, the following functions are limited: • No Wake-up feature / Cyclic Sense • No Digital Input • No Analog Input and conversion via ADC Freescale Semiconductor R CC15 CC14 CC7 CC6 CC5 W R ...
Page 56
... Reset Mode The MM912F634 analog die enters Reset mode if a reset condition occurs (POR - Power On Reset, LVR- Low Voltage Reset, Low Voltage VDDX Reset - LVRX, WDR - Watchdog Reset, EXR - External Reset, and WUR - Wake-up Sleep Reset). Freescale Semiconductor Power Down Power Up ...
Page 57
... After Wake-up from the sources listed above, the device will transit to Normal mode. Reset will wake up the device directly to Reset mode. See Section 4.8, “Wake-up / Cyclic Sense" Freescale Semiconductor after the reset condition is gone. After this delay, the RESET_A RST and VDDX>V LVR timeout is implemented. Once VDD < ...
Page 58
... LSx HSx ADC D2D Lx OFF PTBx LIN Watchdog VSENSE CSENSE Cyclic Sense Note: 62. If configured. 63. Special init through non window watchdog. Freescale Semiconductor for details. Normal full full full full full full full full full (63) full full full not active Modes of Operation ...
Page 59
... Sleep Mode. Will initiate transition to Sleep Mode Normal Mode. Note: 65. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (f ) delay are required between WSR read and MCR write. BASE Freescale Semiconductor ...
Page 60
... HTI - High Temperature Interrupt measured between the VDD and VDDX regulators • Over-temperature Shutdown measured between the VDD and VDDX regulators Freescale Semiconductor VSENSE". In addition, the VS1 supply can be routed to the Section 4.23, “Internal Supply Voltage Sense - BANDGAP" not recommended to connect additional loads to this pin. See ADC2p5 ADC" ...
Page 61
... VDD (2.5 V). External capacitors (C VDD 4.4.2 Power Up Behavior / Power Down Behavior To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 18 shows a standard power up and power down sequence. Freescale Semiconductor HVI HS1 & HS2 LVI bg1p25sleep HSUP (18V) VDDX (5V) ...
Page 62
... Once VDDX has reached the V pulled down to discharge any VDD capacitance (5). RESET_A is activated as well. • The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. Freescale Semiconductor VSUP VDDX Figure 18. Power Up / Down Sequence threshold (1) ...
Page 63
... Once VDDX has reached the V pulled down to discharge any VDD capacitance (5). RESET_A is activated as well. • The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. Freescale Semiconductor NOTE VSUP VDDX Figure 19 ...
Page 64
... Low Voltage Interrupt Enable — Enables the interrupt for the VS1 - Low Voltage Warning. LVIE 0 - Low Voltage Interrupt is disabled 1 - Low Voltage Interrupt is enabled 0 Low Battery Interrupt Enable — Enables the interrupt for the VSENSE - Low Battery Voltage Warning. LBIE 0 - Low Battery Interrupt is disabled 1 - Low Battery Interrupt is enabled Freescale Semiconductor VROVIE HTIE 0 0 ...
Page 65
... Low Voltage Condition present. 0 Low Battery Condition - This status bit indicates a low voltage warning for VSENSE is present. Reading the register will clear LBC the LBI flag if present. See Low Battery Condition present Low Battery Condition present. Freescale Semiconductor VROVC HTC 0 ...
Page 66
... While in Normal or Stop mode, D2DCLK acts as input only with pull present. D2D[3:0] operates as an input/output with pull-down always present. D2DINT acts as output only. 4.5.2.2 Sleep Mode While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption. Freescale Semiconductor Operation". NOTE Die to Die Interface - Target . ...
Page 67
... HOT LSOT HSOT LINOT W Note: 68. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor NOTE SCI RX TX ERR Access: User read 6 5 ...
Page 68
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 81. IVR - Register Field Descriptions Field 5:0 Represents the highest prioritized interrupt pending. See IRQ The following table is listing all MM912F634 analog die interrupt sources with the corresponding priority. Freescale Semiconductor Description IRQ Description Table 82 In case no interrupt is pending, the result will be 0 ...
Page 69
... Section 4.4, “Power Supply" 4.6.2.5 TIM Channel 0 Interrupt (CH0) See Section 4.18, “Basic Timer Module - TIM Freescale Semiconductor Interrupt Source Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. for details on the Voltage Status Register including masking information. for details on the Voltage Status Register including masking information. ...
Page 70
... High Voltage Interrupt (HVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" Freescale Semiconductor (TIM16B4C)". (TIM16B4C)". (TIM16B4C)". (TIM16B4C)". (S08SCIV4)". (S08SCIV4)". ...
Page 71
... Any incorrect serving if the MM912F634 analog die Watchdog will result in a Watchdog Reset. Please refer to the “Window Watchdog" for details. Freescale Semiconductor for details on the Voltage Status Register including masking information. or the MM912F634 analog die was powered up, the POR condition POR , the Low Voltage Reset condition becomes present ...
Page 72
... As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. Reading the Reset Status register will clear the information inside. Writing has no effect. LVR and LVRX are masked when POR or WUR are set. Freescale Semiconductor ...
Page 73
... Wake-up Control Register (WCR) must be configured with appropriate LxWE inputs enabled or disabled before entering low power mode. The Lx - Wake-up may be combined with the Forced Wake-up. Note: Selecting a Lx Input for wake-up will disable a selected analog input once entering low power mode. Freescale Semiconductor Wake Up Cyclic Sense / Forced ...
Page 74
... Wake-up with immediate transition to Reset mode. In this case, the LVR or EXR bits in the Reset Status Register will indicate the source of the event. 4.8.1.7 Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only) While in Sleep mode, a supply voltage VS1 < V Freescale Semiconductor NOTE will result in a transition to Power On mode. POR Wake-up / Cyclic Sense ...
Page 75
... Wake-up Input 2 Enabled - L2 Wake-up Select Bit Wake-up Disabled Wake-up Enabled 1 - L1WE Wake-up Input 1 Enabled - L1 Wake-up Select Bit Wake-up Disabled Wake-up Enabled 0 - L0WE Wake-up Input 0 Enabled - L0 Wake-up Select Bit Wake-up Disabled Wake-up Enabled Freescale Semiconductor L5WE L4WE L3WE Description Section 4.8.2.2, “ ...
Page 76
... Sense Timing = 1000 ms) Note: 74. Cyclic Sense Timing with Accuracy CS Freescale Semiconductor 5 4 FWM 0 0 Description - and ACT Wake-up / Cyclic Sense ...
Page 77
... Reading the WSR will clear the wake-up status bit(s). Writing will have no effect. The Wake-up Source Register (WSR) has to be read after a wake-up condition, in order to execute a new STOP mode command. Two base clock cycles (f required between the WSR read and the MCR write. Freescale Semiconductor 5 4 ...
Page 78
... The WDSR register will reset to default once the watchdog is disabled. Once the watchdog is re-enabled, the initial watchdog sequence has to be performed. During Low Power mode, the Watchdog clock is halted and the Watchdog Service Register (WDSR) is reset to the default state. Freescale Semiconductor ) operating independent from the MCU based D2DCLK clock. The watchdog timeout BASE ...
Page 79
... Table 94. WDSR - Register Field Descriptions Field 7-0 Watchdog Service Register - Writing this register with the correct value (0xAA alternating 0x55) while the window is open WDSR will reset the watchdog counter. Writing the register while the watchdog is disabled will have no effect. Freescale Semiconductor ...
Page 80
... Hall Supply Over-temperature Condition present. During the event, the Hall Supply is shut down. Reading the register will clear the HOT flag if present. See 0 - HSUPON Hall Supply On Hall Supply Regulator disabled 1 - Hall Supply Regulator enabled Freescale Semiconductor is recommended for operation. HSUP ...
Page 81
... Sleep And Stop Mode The high side drivers can be enabled to operate in Sleep and Stop mode for cyclic sensing. See Sense" 4.11.6 PWM Capability Section 4.13, “PWM Control Module (PWM8B2C)" Freescale Semiconductor High Side Drivers - HS Section 4.8, “Wake-up / Cyclic MM912F634 81 ...
Page 82
... PWM Enable for HS1 0 - PWM disabled on HS1 1 - PWM enabled on HS1 (Channel as selected with PWMCS1 HS2 HS2 Control 0 - HS2 disabled 1 - HS2 enabled 0 - HS1 HS2 Control 0 - HS1 disabled 1 - HS1 enabled Freescale Semiconductor PWMCS2 PWMCS1 PWMHS2 Description for the Voltage Status Register. ...
Page 83
... When the High Side is in OFF state, the Open Load Detection function is not operating. When reading the HSSR register while the High Side is operating in PWM and is in the OFF state, the HS1OL and HS2OL bits will not indicate Open Load. Freescale Semiconductor 5 ...
Page 84
... Vreg high voltage VDD Digital LSCEN[3:0] 4.12.1.2 Modes of Operation The Low Side module is active only in Normal mode; the Low Side drivers are disabled in Sleep and Stop mode. Freescale Semiconductor PWMCSx PWMLSx Low Side - Driver (active clamp) on/off open load detection current limitation ...
Page 85
... PWM Channel 0 selected as PWM Channel 1 - PWM Channel 1 selected as PWM Channel 4 - PWMCS1 PWM Channel Select LS1 0 - PWM Channel 0 selected as PWM Channel 1 - PWM Channel 1 selected as PWM Channel Freescale Semiconductor Table 101 shows all the pins and their functions that are I/O Description O Low Side Power Output Driver, Active Clamping ...
Page 86
... Table 107. Low Side Enable Register (LSEN) (85) Offset 0x32 Reset 0 0 Note: 85. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Description LS2CL 0 0 Description for details. (84) (84 ...
Page 87
... Field 3-0 Low Side Control Enable - To allow the LS Control via LSx, the correct value has to be written into the LSCEN Register. LSCEN 0x5 - Low Side Control Enabled all other values - Low Side Control Disabled Freescale Semiconductor Low Side Drivers - LSx Description MM912F634 87 ...
Page 88
... If the bit LSM is set in the Interrupt Mask Register (IMR) than an Interrupt (IRQ) is generated. A write to the Low Side Control Register (LSCR) will re-enable the Low Side drivers when the over-temperature condition is gone. Freescale Semiconductor NOTE for details. The default trim is worst case ...
Page 89
... Functional Description and Application Information 4.12.5 PWM Capability See Section 4.13, “PWM Control Module Freescale Semiconductor (PWM8B2C)". Low Side Drivers - LSx MM912F634 89 ...
Page 90
... Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies • Programmable clock select logic 4.13.1.2 Modes of Operation The PWM8B2C module does operate in Normal mode only. Freescale Semiconductor PWM Control Module (PWM8B2C) and Section 4.17, “General Purpose I/O - (Section 4.11, PTB[0…2]") MM912F634 ...
Page 91
... Die 2 Die Interface Clock. 4.13.2.2 PWM1 — Pulse Width Modulator Channel 1 This signal serves as waveform output of PWM channel 1. 4.13.2.3 PWM0 — Pulse Width Modulator Channel 0 This signal serves as waveform output of PWM channel 0. Freescale Semiconductor PWM Channels PWM Clock Enable Channel 1 Polarity Period and Duty ...
Page 92
... Table 110. PWM Control Register (PWMCTL) (87) Offset 0x60 CAE1 CAE0 W Reset 0 0 Note: 87. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor CAE0 PCLK1 PCLK0 PCKB2 PCKB1 PCKB0 ...
Page 93
... Register bits PCLK0 and PCLK1 can be written anytime clock select changes while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Each PWM channel has a choice of two clocks to use as the clock source for that channel as described by the following. Freescale Semiconductor PWM Control Module (PWM8B2C) Description NOTE ...
Page 94
... Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channel 0. These three bits PCKA[2:0] determine the rate of clock A, as shown in Table 114. Clock B Prescaler Selects PCKB2 Freescale Semiconductor NOTE and Section 4.13.4.2.6, “Center Aligned Outputs"” NOTE PCKB1 PCKB0 0 0 ...
Page 95
... PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock PWMSCLB) Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Freescale Semiconductor PCKA1 PCKA0 Value of Clock A ...
Page 96
... R Bit Reset 0 0 Note: 91. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor NOTE Section 4.13.4.2.5, “Left Aligned Outputs"” Section 4.13.4.2.4, “PWM Timer ...
Page 97
... R Bit Reset 0 0 Note: 92. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor NOTE for more information. Section 4.13.4.2.7, “PWM Boundary PWM Control Module (PWM8B2C) Cases" ...
Page 98
... Offset 0x68/0x69 Bit Reset 0 0 Note: 93. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor NOTE for more information. NOTE Section 4.13.4.2.7, “PWM Boundary PWM Control Module (PWM8B2C) Cases" ...
Page 99
... The scaled B clock uses clock input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Freescale Semiconductor PWM Control Module (PWM8B2C) MM912F634 ...
Page 100
... Functional Description and Application Information Prescale Freescale Semiconductor Clock A Clock A/2, A/4, A/6,....A/512 Count = 1 8-Bit Down Counter Load PWMSCLA DIV 2 Clock B Clock B/2, B/4, B/6,....B/512 Count = 1 8-Bit Down U Counter X Load PWMSCLB DIV 2 Scale Figure 25. PWM Clock Select Block Diagram PWM Control Module (PWM8B2C) ...
Page 101
... The duty is controlled by a match between the duty register and the counter value, and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown in block diagram for the PWM timer. Freescale Semiconductor PWM Control Module (PWM8B2C) NOTE ...
Page 102
... PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. Freescale Semiconductor Reset 8-bit Compare = ...
Page 103
... PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. The counter is cleared at the end of the effective period (see “Center Aligned Outputs"” for more details). Freescale Semiconductor NOTE NOTE Figure 26 and described in Outputs" ...
Page 104
... Clock Source = E, where kHz (100 µs period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 kHz/4 = 2.5 kHz PWMx Period = 400 µs PWMx Duty Cycle = 3/4 *100% = 75% Freescale Semiconductor Counter Counts Counts from last value in PWMCNTx. NOTE Figure 26. When the PWM counter matches the duty register the output flip-flop Figure 26, as well as performing a load from the double buffer period and Section 4.13.4.2.3, “ ...
Page 105
... PWMx Duty Cycle (high time period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% Freescale Semiconductor Figure 28. Duty Cycle = 75% Period = 400 µs NOTE Duty"”. The counter counts from the value in the period register and then back ...
Page 106
... All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured counter out of reset. • All the channels are disabled and all the counters do not count. 4.13.6 Interrupts The PWM module has no Interrupts. Freescale Semiconductor DUTY CYCLE = 75% PERIOD = 800 µs PWMPERx PPOLx >$00 1 >$00 ...
Page 107
... When an under-voltage occurs on VS1 (LVI), the LIN stays in recessive mode if it was in recessive state was in a dominant state, it waits until the next dominant to recessive transition, then it stays in the recessive state. Freescale Semiconductor Section 4.17, “General Purpose I/O - PTB[0…2]" Immunity". ...
Page 108
... LIN will stay functional even with a VS1 under-voltage condition 2 - LINEN LIN Module Enable 0 - LIN Module Disabled 1 - LIN Module Enabled 1-0 - LINSR LIN - Slew Rate Select 00 - Normal Slew Rate (20 kBit Slow Slew Rate (10.4 kBit Fast Slew Rate (100 kBit Normal Slew Rate (20 kBit) Freescale Semiconductor LVSD Description ...
Page 109
... Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity 4.15.1.2 Modes of Operation See Section 4.15.3, “Functional Description",” For details concerning SCI operation in these modes: • 8- and 9-bit data modes • Loop mode • Single-wire mode Freescale Semiconductor Serial Communication Interface (S08SCIV4) MM912F634 109 ...
Page 110
... Functional Description and Application Information 4.15.1.3 Block Diagram Figure 31 shows the transmitter portion of the SCI. INTERNAL BUS M 1 BAUD RATE CLOCK PE PT SBK TXDIR BRK13 Freescale Semiconductor (WRITE-ONLY) SCID – Tx BUFFER 11-BIT TRANSMIT SHIFT REGISTER SHIFT DIRECTION T* PARITY ...
Page 111
... INTERNAL BUS 16 BAUD RATE CLOCK FROM TRANSMITTER LOOPS SINGLE-WIRE LOOP CONTROL RSRC FROM RxD RX- DATA RECOVERY ACTIVE EDGE DETECT PE PT Freescale Semiconductor (READ-ONLY) DIVIDE SCID – Rx BUFFER BY 16 11-BIT RECEIVE SHIFT REGISTER M LBKDE WAKEUP ILT LOGIC RDRF RIE IDLE ...
Page 112
... SCI baud rate generator. When the SCI baud rate generator is disabled to reduce supply current. When 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Freescale Semiconductor Serial Communication Interface (S08SCIV4) of this data sheet for the absolute address assignments for all SCI registers. ...
Page 113
... Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number the data character, including the parity bit, is odd. Even parity means the total number the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. Freescale Semiconductor Serial Communication Interface (S08SCIV4 ...
Page 114
... BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Refer to 0 Normal transmitter operation. 1 Queue break character( sent. Freescale Semiconductor RIE ...
Page 115
... NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and then read the SCI data register (SCID noise detected. 1 Noise detected in the received character in SCID. Freescale Semiconductor Serial Communication Interface (S08SCIV4 ...
Page 116
... Break character detection disabled 1 Break character detection enabled Note: 102. Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle. Freescale Semiconductor Serial Communication Interface (S08SCIV4) Description ...
Page 117
... Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests. PEIE 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when Note: 104. Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle. Freescale Semiconductor Serial Communication Interface (S08SCIV4 (94) TXDIR ...
Page 118
... For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ±4.0 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates normally possible to get within a few percent, which is acceptable for reliable communications ...
Page 119
... TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below. Table 139. Break Character Length BRK13 Freescale Semiconductor Figure 31. M Break Character Length ...
Page 120
... RWU all receivers wake up in time to look at the first character(s) of the next message. Freescale Semiconductor (Figure 32) is used as a guide for the overall receiver functional description. Next, the Section 4.15.3.4, “ ...
Page 121
... If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE condition is lost. Freescale Semiconductor Serial Communication Interface (S08SCIV4) MM912F634 ...
Page 122
... When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. Freescale Semiconductor Serial Communication Interface (S08SCIV4) MM912F634 ...
Page 123
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 143. LXCR - Register Field Descriptions Field 5-0 Analog Input Divider Ratio Selection - Lx L[5-0] (typ 7.2 (typ) Freescale Semiconductor Section 4.8, “Wake-up / Cyclic Description ...
Page 124
... Alternative PWM Functionality As an alternative routing for the PWM channel ( output, the PortB 2 (PTB2) can be configured to output one of the two PWM channels defined in the Section 4.13, “PWM Control Module configured in the Port B Configuration Register 2 (PTBC2). Freescale Semiconductor PTB2 PTB1 AD2 AD1 ...
Page 125
... Mode 1, SCI connected to PTB0 and PTB1 (external SCI mode Mode 2, LIN Physical Layer Interface connected to PTB0 and PTB1 (external LIN mode Mode 3, SCI internally connected the LIN Physical Layer Interface and PTB0 and PTB1 are connected both as outputs (Observe mode) Freescale Semiconductor ...
Page 126
... Table 150. PTB - Register Field Descriptions Field 2-0 Port B general purpose input/output data — Data Register PTB[2-0] If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered and synchronized pin input state is read. Freescale Semiconductor ...
Page 127
... Block Diagram D2D Clock Timer overflow interrupt Timer channel 0 interrupt Timer channel 3 interrupt For more information see the respective functional descriptions see Freescale Semiconductor Prescaler Channel 0 16-bit Counter Channel 1 Channel 2 Channel 3 Registers Figure 35. Timer Block Diagram Section 4.18.4, “Functional Description" Basic Timer Module - TIM (TIM16B4C) ...
Page 128
... Offset 0xC0 Timer Input Capture/Output Compare Select (TIOS) 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 Freescale Semiconductor NOTE Functionality". NOTE Section 4.18.6, “Interrupts". Table 151. Use Timer Compare Force Register (CFORC) Output Compare 3 Mask Register (OC3M) Output Compare 3 Data Register (OC3D) ...
Page 129
... Always read $00. 113. Only writable in special modes. (Refer to SOC Guide for different modes). 114. Write to these registers have no meaning or effect during input capture. Freescale Semiconductor Use Timer Control Register 1 (TCTL1) Timer Control Register 2 (TCTL2) Timer Interrupt Enable Register (TIE) Timer System Control Register 2 (TSCR2) ...
Page 130
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 155. CFORC - Register Field Descriptions Field 3-0 Force Output Compare Action for Channel 3-0 FOC[3- Force Output Compare Action disabled. Input Capture or Output Compare Channel Configuration 1 - Force Output Compare Action enabled Freescale Semiconductor IOS3 0 ...
Page 131
... Table 158. Output Compare 3 Data Register (OC3D) (118) Offset 0xC3 Reset 0 0 Note: 118. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor NOTE NOTE OC3M3 Description NOTE 5 4 ...
Page 132
... Table 162. Timer System Control Register 1 (TSCR1) (120) Offset 0xC6 TEN W Reset 0 0 Note: 120. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Description NOTE tcnt13 tcnt12 tcnt11 tcnt5 ...
Page 133
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 165. TTOV - Register Field Descriptions Field 3-0 Toggle On Overflow Bits TOV[3- Toggle output compare pin on overflow feature enabled Toggle output compare pin on overflow feature disabled. Freescale Semiconductor Description NOTE ...
Page 134
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 170. TCTL2 - Register Field Descriptions Field EDGnB,EDGnA Input Capture Edge Control These four pairs of control bits configure the input capture edge detector circuits. Freescale Semiconductor NOTE ...
Page 135
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 175. TIE - Register Field Descriptions Field 7 Timer Overflow Interrupt Enable TOI 1 = Hardware interrupt requested when TOF flag set in TFLG2 register Hardware Interrupt request inhibited. Freescale Semiconductor EDGnA Configuration 0 Capture disabled 1 Capture on rising edges only 0 ...
Page 136
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 178. TFLG1 - Register Field Descriptions Field 3-0 Input Capture/Output Compare Channel Flag. C[3:0 Input Capture or Output Compare event occurred event (Input Capture or Output Compare event) occurred. Freescale Semiconductor Description PR1 PR0 ...
Page 137
... W Reset tc0_7 tc0_6 W Reset 0 0 Note: 128. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor NOTE Description NOTE tc0_13 tc0_12 tc0_11 ...
Page 138
... Reset 0 0 Note: 131. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 185. TCn - Register Field Descriptions Field 15-0 16 Timer Input Capture/Output Compare Registers tcn[15-0] Freescale Semiconductor tc1_13 tc1_12 tc1_11 ...
Page 139
... COMPARATOR TC3 EDG3A EDG3B 4.18.4.2 Prescaler The prescaler divides the bus clock 16, 32, 64, or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in the timer system control register 2 (TSCR2). Freescale Semiconductor D2D Clock CxI CxF CLEAR COUNTER TOF TOI TE ...
Page 140
... This section describes interrupts originated by the TIM16B4C block. communicate with the MCU. Table 186. TIM16B4C Interrupts Interrupt Offset Vector C[3:0 TOF - - Freescale Semiconductor Table 186 lists the interrupts generated by the TIM16B4C to Priority Source - Timer Channel 3-0 - Timer Overflow Basic Timer Module - TIM (TIM16B4C) 4.18.3, “Memory Map and Registers“, which ...
Page 141
... This active high output will be asserted by the module to request a timer overflow interrupt, following the timer counter overflow when the overflow enable bit (TOI) bit of TFLG2 register is set. This interrupt is serviced by the system controller. Freescale Semiconductor Basic Timer Module - TIM (TIM16B4C) Section 4.6, “Interrupts" ...
Page 142
... Sequence- and Continuous Conversion Mode with IRQ for Sequence Complete indication • Dedicated Result register for each channel 4.19.2 Modes of Operation The Analog Digital Converter Module is active only in normal mode disabled in Sleep and Stop mode. Freescale Semiconductor A/D Control Logic (ADC Wrapper) A Registers DATAA2D ...
Page 143
... ADR1[1:0] 0x89 ADR1 (lo 0x8A ADR2 (hi ADR2[1:0] 0x8B ADR2 (lo 0x8C ADR3 (hi) W Freescale Semiconductor Table 187 Description Analog Ground Connection Analog Digital Converter Regulator Filter Terminal. A capacitor C required for operation OCE ADCRST 0 0 CCNT3 0 CH12 CH11 CH5 CH4 ...
Page 144
... ADR10 (lo 0x9C ADR11 (hi ADR11[1:0] 0x9D ADR11 (lo 0x9E ADR12 (hi ADR12[1:0] 0x9F ADR12 (lo 0xA0 Reserved W R 0xA1 Reserved W Freescale Semiconductor ADR4[9:2] ADR5[9:2] ADR6[9:2] ADR7[9:2] ADR8[9:2] ADR9[9:2] ADR10[9:2] ADR11[9:2] ADR12[9:2] Analog Digital Converter - ADC 2 1 Bit 0 MM912F634 144 ...
Page 145
... Continuous Conversion Enable 0 - Continuous Conversion Disabled 1 - Continuous Conversion Enabled 5 - OCE Offset Compensation Enable 0 - Offset Compensation Disabled 1 - Offset Compensation Enabled, This feature requires the CH15 bit in the ADC Conversion Control Register (ACCR set for all conversions. Freescale Semiconductor ADR14[9:2] ADR15[9:2] NOTE 5 ...
Page 146
... R 0 CH15 CH14 CH12 W Reset Note: 135. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Description CCNT3 Description CH11 CH10 ...
Page 147
... ADC - Channel X left adjusted Result Register. Reading the register will clear the corresponding CCx register in the ACCSR ADRx register. 16-bit read recommended. 8-Bit read: Reading the low byte will latch the high byte for the next read, reading the high byte will clear the cc flag. Freescale Semiconductor Description 11 10 ...
Page 148
... To activate the Offset compensation feature, the OCE bit in the ADC Config Register (ACR) has to be set, and the CH15 has to be enabled when starting a new conversion, by writing to the ADC Conversion Control Register (ACCR). The compensation will work with single and sequence conversion. Freescale Semiconductor Description (138) Trimming" ...
Page 149
... Example 2. Sequence of Channel 10 (VSENSE) + Channel 15 (Offset Compensation) 1c (count (sample Ch15) + 18c (conversion Ch15 (in between (count further to Ch10 is performed while converting ch15 (sample) + 18c (conversion cycles from start to end of both conversions. Freescale Semiconductor MCU – IFR (4C..4F) => CTR0..3 OCE – Offset Compensation Enable = 1 ACCR – ...
Page 150
... Table 200. Current Sense Register (CSR) (139) Offset 0x3C CSE W Reset 0 0 Note: 139. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor G G ...
Page 151
... Note: 140. This feature should be used when implementing an external filter to the current sense ISENSEx inputs. In principal an internal charge compensation is activated in synch with the conversion to avoid the sample capacitors to be discharged by the external filter. Freescale Semiconductor Current Sense Module - ISENSE Description (140) ...
Page 152
... Analog Digital Converter (Channel 11 2.5 2.0 1.5 1.0 0,15V -50°C Typ. 0.5 -50°C Refer to the Section 4.19, “Analog Digital Converter - ADC" Freescale Semiconductor 0°C 50°C 100°C Figure 40. TSENSE - Graph for details on the channel selection and analog measurement. Temperature Sensor - TSENSE 1,984V 150°C Typ. T 150°C MM912F634 152 ...
Page 153
... CH14 the 2p5sleep Bandgap circuity. Note: 141. The maximum allowed sample frequency for Channel 14 is limited to fCH14. Increasing the sample frequency above can result in unwanted turn off of the LS drivers due to a false VREG over-voltage. Freescale Semiconductor NOTE LBI Prescaler CH11 VSENSE ...
Page 154
... Table 203. MM912F634 - MCU vs. Analog Die Trimming Register Correlation Name CTR0 CTR1 CTR2 CTR3 Note: 143. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor NOTE (Section 4.28.2.2.4, “MMC Control Register LINTR WDCTRE ...
Page 155
... Table 206. Trimming Register 1 (CTR1) (145) Offset 0xF1 BGTRE CTR1_6 W Reset 0 0 Note: 145. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor WDCTRE CTR0_4 CTR0_3 Description BGTRIMUP BGTRIMDN ...
Page 156
... Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 209. CTR2 - Register Field Descriptions Field 4 Sleep Bandgap trim enable SLPBGTRE 0 no trim can be done 1 trim lock can be done by setting SLPBGTR[2:0] bits and SLPBG_LOCK bit 3 bg1p25sleep trim lock bit SLPBG_LOCK Freescale Semiconductor Description SLPBGTRE SLPBG_LOCK ...
Page 157
... Spare Trim enable bit CTR3_E 2 Spare Trim bit 2 CTR3_2 1 Spare Trim bit 1 CTR3_1 0 Spare Trim bit 0 CTR3_0 Freescale Semiconductor Description OFFCTR1 OFFCTR0 CTR3_E Description MM912F634 - Analog Die Trimming Access: User read/write CTR3_2 ...
Page 158
... Configurable drive strength on all output pins • Die 2 Die Initiator (D2DI) — 2.0 Mbyte/s data rate — Configurable 4-bit or 8-bit wide data path • 20 MHz maximum CPU bus frequency (16 MHz for MM912F634CV2AP) Freescale Semiconductor MM912F634 - MCU Die Overview MCU ANALOG MM912F634 158 ...
Page 159
... Device Memory Map 4.26.3.1 Address Mapping Figure 44 shows S12S CPU & BDM local address translation to the global memory map. It also indicates the location of the internal resources in the memory map. Freescale Semiconductor CPU12 Die-to-Die Initiator Debug Module 2 address breakpoints scalable bits wide ...
Page 160
... Write access to Reserved has no effect. Read access will return always 0x0000. 149. RAMSIZE is the hexadecimal value of RAM SIZE in bytes. 150. Accessing unimplemented FLASH pages causes an illegal address reset. 151. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes. Freescale Semiconductor Bottom Address 0x0_0000 0x0_0400 0x0_0800 FLASH_LOW = (151) ...
Page 161
... Unpaged 16K FLASH 0x4000 Unpaged 16K FLASH 0x8000 16K FLASH window 0xC000 Unpaged 16K FLASH Reset Vectors 0xFFFF Freescale Semiconductor RAM_HIGH PPAGE FLASH_LOW Figure 44. MC9S12I32 Global Address Mapping MM912F634 - MCU Die Overview Global Memory Map 0x0_0000 1K REGISTERS 0x0_0400 IFR ...
Page 162
... CRG to all modules. Consult the CRG specification for details on clock generation. EXTAL CRG FLL IRC XTAL COP Freescale Semiconductor Table 213 shows the assigned part ID number and Mask Set number. Mask Set Number 0M33G 1M33G SPI D2DI ...
Page 163
... The MCU features two main low-power modes. Consult the respective module description for module specific behavior in system stop and system wait mode. An important source of information about the clock system is the Clock and Reset Generator description (CRG). Freescale Semiconductor 4.26.6.1 Chip Configuration 4.26.6.2.4 Freeze Mode ...
Page 164
... System reset or illegal access reset $FFFC $FFFA Vector base + $F8 Vector base+ $F6 Vector base+ $F4 Vector base+ $F2 Freescale Semiconductor 4.27, “Port Integration Module (9S12I32PIMV1)“ Interrupt Source Oscillator monitor reset COP watchdog reset Unimplemented instruction trap SWI D2DI Error Interrupt D2DI External Error Interrupt ...
Page 165
... When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective block descriptions for register reset states. 4.26.8.3.1 I/O Pins Refer to the 4.27, “Port Integration Module (9S12I32PIMV1)“ 4.26.8.3.2 Memory The RAM array is not initialized out of reset. Freescale Semiconductor CCR Interrupt Source Mask Real time interrupt I bit SPI I bit CRG FLL lock ...
Page 166
... Reserved 0x0002 DDRA 0x0003 Reserved 0x0004 PTC W R 0x0005 PTD7 PTD6 PTD W Freescale Semiconductor PTA5 PTA4 PTA3 DDRA5 DDRA4 DDRA3 PTD5 PTD4 PTD3 Port Integration Module (9S12I32PIMV1 Bit 0 PTA2 ...
Page 167
... W Reserved 0x0120 PTIA 0x0121 Reserved 0x0122 RDRA W 0x0123 0x01FF W Reserved Freescale Semiconductor DDRD5 DDRD4 DDRD3 PTIA5 PTIA4 PTIA3 RDRA5 RDRA4 RDRA3 Port Integration Module (9S12I32PIMV1 Bit 0 0 ...
Page 168
... When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered and synchronized pin input state is read. Freescale Semiconductor ...
Page 169
... Associated pin is configured as high-impedance input. 4.27.3.4 PIM Reserved Register Table 222. PIM Reserved Register Address 0x0003 Reset 0 0 Note: 157. Read: Anytime. Write: Unimplemented. Writing to this register has no effect. Freescale Semiconductor DDRA5 DDRA4 DDRA3 0 0 ...
Page 170
... When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered and synchronized pin input state is read. Freescale Semiconductor ...
Page 171
... The D2DI function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input. Freescale Semiconductor ...
Page 172
... PIM Reserved Register Table 234. PIM Reserved Register Address 0x0121 Reset 0 0 Note: 165. Read: Anytime. Write: Unimplemented. Writing to this register has no effect. Freescale Semiconductor PTIA5 PTIA4 PTIA3 u u ...
Page 173
... Full drive strength enabled. 4.27.3.13 PIM Reserved Registers Table 237. PIM Reserved Register Address 0x0123-0x017F Reset 0 0 Note: 167. Read: Anytime. Write: Unimplemented. Writing to these registers has no effect. Freescale Semiconductor RDRA5 RDRA4 RDRA3 Description ...
Page 174
... Input register (PTIx) This is a read-only register and always returns the buffered and synchronized state of the pin 4.27.4.2.4 Reduced drive register (RDRx) If the pin is used as an output this register allows the configuration of the drive strength. Periph. Module Freescale Semiconductor PTIx synch PTx 0 ...
Page 175
... It is not recommended to write PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. Freescale Semiconductor Port Integration Module (9S12I32PIMV1) ...
Page 176
... MCU security control • Separate memory map schemes for each master CPU, BDM • Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes Freescale Semiconductor Memory Mapping Control (S12SMMCV1) MM912F634 176 ...
Page 177
... In normal and special single chip mode the internal memory is used. 4.28.1.5 Block Diagram Figure 47 shows a block diagram of the MMC. BDM MMC Figure 47. MMC Block Diagram External Signal Description Freescale Semiconductor Address Decoder & Priority Target Bus Controller FLASH RAM Memory Mapping Control (S12SMMCV1) CPU DBG ...
Page 178
... Read: Anytime Write: Anytime These four index bits are used to page 16 kByte blocks into the Flash page window located in the local (CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see Freescale Semiconductor Description Mode input Figure 48. Detailed descriptions of the registers and bits Figure 48 ...
Page 179
... Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. Freescale Semiconductor Global Address [17:0] Bit13 Bit14 Address [13:0] Address: CPU Local Address or BDM Local Address Figure 49 ...
Page 180
... Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. DP[15:8] The bits from this register form bits [15:8] of the address (see Bit17 Bit16 Example 1. This Example Demonstrates Usage of the Direct Addressing Mode MOVB #0x80,DIRECT LDY <00 Freescale Semiconductor Description Figure 50). Global Address [17:0] Bit15 Bit8 Bit7 DP [15:8] CPU Address [15:0] Figure 50. Direct Address Mapping ...
Page 181
... Changes of operating modes are not allowed when the device is secured, but it will block further writes to the register bit except in special modes. Normal 1 Single-Chip RESET (NS) 1 Transition done by external pins (MODC) RESET Transition done by write access to the MODE register Figure 51. Mode Transition Diagram when MCU is Unsecured Freescale Semiconductor Figure 51). ...
Page 182
... CPU begins execution of firmware commands or the BDM begins execution of hardware commands. The resources which share memory space with the BDM module will not be visible in the memory map during active BDM mode. Freescale Semiconductor Figure 52. MMC Control Register (MMCCTL1) 5 ...
Page 183
... The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing a firmware command which uses CPU instructions BDM hardware commands. See the BDM Block Guide for further details. (see Figure 53). Freescale Semiconductor Memory Mapping Control (S12SMMCV1) Section 4.28.4.1, “CALL and RTC MM912F634 183 ...
Page 184
... Refer to the Device User Guide for further details. Figure 44 that the memory spaces have fixed top addresses. Freescale Semiconductor BDM HARDWARE COMMAND Global Address [17:0] Bit13 Bit14 ...
Page 185
... BDM accesses to the unimplemented areas are allowed but the data will be undefined. No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block Guide). Freescale Semiconductor Memory Mapping Control (S12SMMCV1) Bottom Address 0x0_0000 ...
Page 186
... RAM Unpaged 16K FLASH 0x4000 Unpaged 16K FLASH 0x8000 16K FLASH window 0xC000 Unpaged 16K FLASH Reset Vectors 0xFFFF Freescale Semiconductor 0x0_0000 0x0_0400 0x0_0800 RAM_HIGH 0x3_0000 0x3_4000 PPAGE 0x3_8000 0x3_C000 0x3_FFFF Figure 54. Local to Global Address Mapping Memory Mapping Control (S12SMMCV1) ...
Page 187
... FLASH 0x4000 Unpaged 16K FLASH 0x8000 16K FLASH window 0xC000 Unpaged 16K FLASH Reset Vectors 0xFFFF Figure 55. Implemented Global Address Mapping Freescale Semiconductor 0x0_0000 0x0_0400 0x0_0800 RAM_HIGH PPAGE FLASH_LOW 0x3_FFFF Memory Mapping Control (S12SMMCV1) Global Memory Map 1K REGISTERS ...
Page 188
... BDM has priority over CPU when its access is stalled for more than 128 cycles. In the later case the CPU will be stalled after finishing the current operation and the BDM will gain access to the bus. 4.28.3.4 Interrupts The MMC does not generate any interrupts Freescale Semiconductor CPU S12X0 MMC “Crossbar Switch” XBUS0 ...
Page 189
... PPAGE register from the stack, functions terminated with the RTC instruction must be called using the CALL instruction even when the correct page is already present in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time of the RTC instruction execution. Freescale Semiconductor Memory Mapping Control (S12SMMCV1) MM912F634 ...
Page 190
... Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 4.29.3.1.1, “Interrupt Vector Base Register (IVBR)"” Freescale Semiconductor Interrupt Module (S12SINTV1) Section 4.29.5.3, “Wake-up from Stop or Wait Section 4.29.5.3, “Wake-up from Stop or Wait for details ...
Page 191
... This section describes in address order all the 9S12I32PIMV1 registers and their individual bits. 4.29.3.1.1 Interrupt Vector Base Register (IVBR) Address: 0x001F Reset 1 1 Read: Anytime Write: Anytime Freescale Semiconductor Figure 57. 9S12I32PIMV1 Block Diagram Figure 58. Interrupt Vector Base Register (IVBR IVB_ADDR[7: Interrupt Module (S12SINTV1) Wake-up CPU Vector Address ...
Page 192
... CPU vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector. 4.29.4.3 Reset Exception Requests The 9S12I32PIMV1 module supports three system reset exception request types (please refer to CRG for details): 1. Pin reset, power-on reset or illegal address reset Freescale Semiconductor Interrupt Module (S12SINTV1) Description NOTE MM912F634 192 ...
Page 193
... An ISR of an interruptible I bit maskable interrupt request could basically look like this: 1. Service interrupt, e.g., clear interrupt flags, copy data, etc. 2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt requests) 3. Process data 4. Return from interrupt by executing the instruction RTI Freescale Semiconductor Interrupt Module (S12SINTV1) Source MM912F634 193 ...
Page 194
... If the I bit in the CCR is set, all I bit maskable interrupts are masked from wake-up the MCU. Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can wake-up the MCU from stop mode. Freescale Semiconductor Interrupt Module (S12SINTV1) MM912F634 ...
Page 195
... General operation of the BDM is available and operates the same in all normal modes. • Special single chip mode In special single chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. Freescale Semiconductor Background Debug Module (S12SBDMV1) MM912F634 195 ...
Page 196
... A block diagram of the BDM is shown in Host Serial System BKGD Interface Register Block TRACE BDMACT ENBDM SDV UNSEC BDMSTS Register Freescale Semiconductor Figure 59. Data 16-Bit Shift Register Control Instruction Code and Execution Standard BDM Firmware LOOKUP TABLE Secured BDM Firmware LOOKUP TABLE Figure 59. BDM Block Diagram Background Debug Module (S12SBDMV1) Section 4 ...
Page 197
... Reserved 0x3_FF05 Reserved W R 0x3_FF06 BDMCCR CCR7 0x3_FF07 Reserved W Freescale Semiconductor Module BDM registers BDM firmware ROM Family ID (part of BDM firmware ROM) BDM firmware ROM Figure 60. Registers are accessed by host-driven Figure 60. BDM Register Summary BDMACT 0 SDV ...
Page 198
... BDM active mode. — All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution. Freescale Semiconductor Figure 60. BDM Register Summary (continued) 6 ...
Page 199
... When entering background debug mode, the BDM CCR holding register is used to save the condition code register of the user’s program also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written to modify the CCR value. Freescale Semiconductor Description 6 ...
Page 200
... Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see Section 4.30.4.3, “BDM Hardware Commands"”), and in secure mode (see can only be executed when the system is not secure and is in active background debug mode (BDM). Freescale Semiconductor ...