SPC5646CCF0MLT1 Freescale Semiconductor, SPC5646CCF0MLT1 Datasheet
SPC5646CCF0MLT1
Specifications of SPC5646CCF0MLT1
Related parts for SPC5646CCF0MLT1
SPC5646CCF0MLT1 Summary of contents
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Freescale Data Sheet: Technical Data MPC5646C Microcontroller Datasheet On-chip modules available within the family include the following features: • e200z4d dual issue, 32-bit core Power Architecture compliant CPU — 120 MHz — 4 KB, 2/4-Way Set Associative Instruction ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction 1.1 Document Overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the MPC5646C device. To ensure a complete understanding of the device functionality, ...
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Feature MPC5644B MPC5644C Package 176 208 176 LQFP LQFP LQFP CPU e200z4d e200z4d + e200z0h 2 Execution speed Up to 120 MHz Up to 120 MHz (e200z4d MHz (e200z0h) Code flash memory 1.5 MB Data flash memory ...
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Table 1. MPC5646C family comparison Feature MPC5644B Package 176 208 176 LQFP LQFP LQFP kHz oscillator (SXOSC) 12 GPIO 147 177 147 Debug JTAG Cryptographic Services Engine (CSE) 1 Feature set dependent on selected peripheral multiplexing; ...
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Block diagram 2 Block diagram Figure 1 shows the detailed block diagram of the MPC5646C. JTAGC JTAG Port Nexus Port Nexus NMI0 Voltage NMI1 regulator NMI0 Interrupt requests from peripheral NMI1 Clocks CMU FMPLL STM RTC/API ...
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Table 2 summarizes the functions of the blocks present on the MPC5646C. Block Analog-to-digital converter (ADC) Converts analog voltages to digital values Boot assist module (BAM) Clock monitor unit (CMU) Cross triggering unit (CTU) Cryptographic Security Engine (CSE) Crossbar (XBAR) ...
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Block diagram Table 2. MPC5646C series block summary (continued) Block LinFlexD (Local Interconnect Network Flexible with DMA support) Memory protection unit (MPU) Clock generation module (MC_CGM) Power control unit (MC_PCU) Reset generation module (MC_RGM) Mode entry module (MC_ME) Non-Maskable Interrupt ...
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Package pinouts and signal descriptions The available LQFP pinouts and the MAPBGA ballmaps are provided in the following figures. For functional port pin description, see Table 4. PB[3] 1 PC[9] 2 PC[14] 3 PC[15] 4 PJ[4] 5 VDD_HV_A 6 ...
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Package pinouts and signal descriptions PB[3] 1 PC[9] 2 PC[14] 3 PC[15] 4 PJ[4] 5 VDD_HV_A 6 VSS_HV 7 PH[15] 8 PH[13] 9 PH[14] 10 P[I6] 11 P[I7] 12 PG[5] 13 PG[4] 14 PG[3] 15 PG[2] 16 PA[2] 17 PE[0] ...
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PC[15] PB[2] PC[13] PI[1] A PH[13] PC[14] PC[8] PC[12] B PH[14] VDD_HV_ PC[9] PL[ PG[5] PI[6] PJ[4] PB[3] PK[15] D PG[3] PI[7] PH[15] PG[2] VDD_LV E PA[2] PG[4] PA[1] PE[1] F PE[8] PE[0] PE[10] ...
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Package pinouts and signal descriptions Fast I = Input only with analog feature A = Analog 3.2 System pins The system pins are listed in Table 3. Port pin Function RESET Bidirectional reset with Schmitt-Trigger characteristics ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PA[1] PCR[1] AF0 AF1 AF2 AF3 — — — PA[2] PCR[2] AF0 AF1 AF2 AF3 — — PA[3] PCR[3] AF0 AF1 AF2 AF3 — — — PA[4] PCR[4] AF0 AF1 ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PA[8] PCR[8] AF0 AF1 AF2 AF3 — — — — PA[9] PCR[9] AF0 AF1 AF2 AF3 — — PA[10] PCR[10] AF0 AF1 AF2 AF3 — ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PA[15] PCR[15] AF0 AF1 AF2 AF3 — PB[0] PCR[16] AF0 AF1 AF2 AF3 PB[1] PCR[17] AF0 AF1 AF2 — — — PB[2] PCR[18] AF0 AF1 AF2 AF3 PB[3] PCR[19] AF0 ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PB[7] PCR[23] AF0 AF1 AF2 AF3 — — PB[8] PCR[24] AF0 AF1 AF2 AF3 — — — — 5 PB[9] PCR[25] AF0 AF1 AF2 AF3 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PB[14] PCR[30] AF0 AF1 AF2 AF3 — PB[15] PCR[31] AF0 AF1 AF2 AF3 — 6 PC[0] PCR[32] AF0 AF1 AF2 AF3 6 PC[1] PCR[33] AF0 AF1 AF2 AF3 PC[2] PCR[34] ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PC[6] PCR[38] AF0 AF1 AF2 AF3 PC[7] PCR[39] AF0 AF1 AF2 AF3 — — PC[8] PCR[40] AF0 AF1 AF2 AF3 PC[9] PCR[41] AF0 AF1 AF2 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PC[14] PCR[46] AF0 AF1 AF2 AF3 ALT4 — PC[15] PCR[47] AF0 AF1 AF2 AF3 ALT4 PD[0] PCR[48] AF0 AF1 AF2 AF3 — — — PD[1] PCR[49] AF0 AF1 AF2 AF3 ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PD[5] PCR[53] AF0 AF1 AF2 AF3 — — PD[6] PCR[54] AF0 AF1 AF2 AF3 — — PD[7] PCR[55] AF0 AF1 AF2 AF3 — — PD[8] ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PD[12] PCR[60] AF0 AF1 AF2 AF3 — PD[13] PCR[61] AF0 AF1 AF2 AF3 — PD[14] PCR[62] AF0 AF1 AF2 AF3 ALT4 — PD[15] PCR[63] AF0 AF1 AF2 AF3 ALT4 — ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PE[3] PCR[67] AF0 AF1 AF2 AF3 — — PE[4] PCR[68] AF0 AF1 AF2 AF3 ALT4 — PE[5] PCR[69] AF0 AF1 AF2 AF3 — — PE[6] ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PE[11] PCR[75] AF0 AF1 AF2 AF3 — — PE[12] PCR[76] AF0 AF1 AF2 AF3 — — — — PE[13] PCR[77] AF0 AF1 AF2 AF3 — PE[14] PCR[78] AF0 AF1 AF2 ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PF[3] PCR[83] AF0 AF1 AF2 AF3 — PF[4] PCR[84] AF0 AF1 AF2 AF3 — PF[5] PCR[85] AF0 AF1 AF2 AF3 — PF[6] PCR[86] AF0 AF1 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PF[11] PCR[91] AF0 AF1 AF2 AF3 — — PF[12] PCR[92] AF0 AF1 AF2 AF3 PF[13] PCR[93] AF0 AF1 AF2 AF3 — — PF[14] PCR[94] AF0 AF1 AF2 AF3 ALT4 PF[15] ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PG[2] PCR[98] AF0 AF1 AF2 AF3 PG[3] PCR[99] AF0 AF1 AF2 AF3 — PG[4] PCR[100] AF0 AF1 AF2 AF3 PG[5] PCR[101] AF0 AF1 AF2 AF3 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PG[10] PCR[106] AF0 AF1 AF2 AF3 — PG[11] PCR[107] AF0 AF1 AF2 AF3 PG[12] PCR[108] AF0 AF1 AF2 AF3 ALT4 PG[13] PCR[109] AF0 AF1 AF2 AF3 ALT4 PG[14] PCR[110] AF0 ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PH[2] PCR[114] AF0 AF1 AF2 AF3 ALT4 PH[3] PCR[115] AF0 AF1 AF2 AF3 ALT4 PH[4] PCR[116] AF0 AF1 AF2 AF3 PH[5] PCR[117] AF0 AF1 AF2 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PH[11] PCR[123] AF0 AF1 AF2 AF3 PH[12] PCR[124] AF0 AF1 AF2 AF3 PH[13] PCR[125] AF0 AF1 AF2 AF3 PH[14] PCR[126] AF0 AF1 AF2 AF3 PH[15] PCR[127] AF0 AF1 AF2 AF3 ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PI[4] PCR[132] AF0 AF1 AF2 AF3 PI[5] PCR[133] AF0 AF1 AF2 AF3 ALT4 PI[6] PCR[134] AF0 AF1 AF2 AF3 ALT4 PI[7] PCR[135] AF0 AF1 AF2 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PI[12] PCR[140] AF0 AF1 AF2 AF3 — PI[13] PCR[141] AF0 AF1 AF2 AF3 — PI[14] PCR[142] AF0 AF1 AF2 AF3 — — PI[15] PCR[143] AF0 AF1 AF2 AF3 — PJ[0] ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PJ[4] PCR[148] AF0 AF1 AF2 AF3 PJ[5] PCR[149] AF0 AF1 AF2 AF3 — PJ[6] PCR[150] AF0 AF1 AF2 AF3 — PJ[7] PCR[151] AF0 AF1 AF2 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PJ[12] PCR[156] AF0 AF1 AF2 AF3 — PJ[13] PCR[157] AF0 AF1 AF2 AF3 — — — — PJ[14] PCR[158] AF0 AF1 AF2 AF3 PJ[15] PCR[159] AF0 AF1 AF2 AF3 — ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PK[4] PCR[164] AF0 AF1 AF2 AF3 PK[5] PCR[165] AF0 AF1 AF2 AF3 — — PK[6] PCR[166] AF0 AF1 AF2 AF3 PK[7] PCR[167] AF0 AF1 AF2 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PK[13] PCR[173] AF0 AF1 AF2 AF3 — PK[14] PCR[174] AF0 AF1 AF2 AF3 PK[15] PCR[175] AF0 AF1 AF2 AF3 — — PL[0] PCR[176] AF0 AF1 AF2 AF3 PL[1] PCR[177] AF0 ...
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Package pinouts and signal descriptions Table 4. Functional port pin descriptions (continued) Port PCR pin PL[7] PCR[183] AF0 AF1 AF2 AF3 PL[8] PCR[184] AF0 AF1 AF2 AF3 — PL[9] PCR[185] AF0 AF1 AF2 AF3 PL[10] PCR[186] AF0 AF1 AF2 AF3 ...
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Table 4. Functional port pin descriptions (continued) Port PCR pin PM[1] PCR[193] AF0 AF1 AF2 AF3 PM[2] PCR[194] AF0 AF1 AF2 AF3 PM[3] PCR[195] AF0 AF1 AF2 AF3 PM[4] PCR[196] AF0 AF1 AF2 AF3 PM[5] PCR[197] AF0 AF1 AF2 AF3 ...
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Electrical Characteristics 7 When MBIST is enabled to run ( STCU Enable = 1), the application must not drive or tie PAD[178) (MDO[0 before the device exits reset (external reset is removed) as the pad is internally ...
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NVUSRO [PAD3V5V(0)] field description Table 6 shows how NVUSRO [PAD3V5V(0)] controls the device configuration for V 1 Value '1' is delivery value part of shadow flash memory, thus programmable by customer. The DC electrical ...
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Electrical Characteristics Table 8. Absolute maximum ratings (continued) Symbol Parameter V SR Voltage on VSS_HV_ADC0, SS_ADC VSS_HV_ADC1 (ADC reference) pin with respect to ground (V SS_HV V SR Voltage on VDD_HV_ADC0 DD_HV_ADC0 with respect to ground (V ) SS_HV 4 ...
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Recommended operating conditions Table 9. Recommended operating conditions (3.3 V) Symbol Parameter V SR Digital ground on VSS_HV SS_HV pins Voltage on V DD_HV_A with respect to ground (V ) SS_HV Voltage on ...
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Electrical Characteristics 2 100 nF EMI capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µF bulk capacitance needs to be provided as CREG on each VDD_LV pin. For details refer to the Power Management chapter of the ...
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Table 10. Recommended operating conditions (5.0 V) (continued) Symbol V SR Voltage on any GPIO pin with IN respect to ground ( Injected input current on any pin INJPAD during overload condition I SR Absolute sum of all ...
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Electrical Characteristics 4.5 Thermal characteristics 4.5.1 Package thermal characteristics Symbol C Parameter Thermal resistance, JA junction-to-ambient natural convection Thermal resistance, JA junction-to-ambient natural convection 1 Thermal characteristics are targets based on simulation that are ...
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Most of the time for the applications configured to continuously drive external modules and/or memories. An approximate relationship between P Therefore, solving equations 1 and 2: Where constant for the particular part, which may be ...
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Electrical Characteristics PDIx = ‘1 (GPDI register of SIUL) PDIx = ‘0’ Figure 5. I/O input DC electrical characteristics definition Table 13. I/O input DC electrical characteristics Symbol C Parameter V SR ...
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Table 14 provides weak pull figures. Both pull-up and pull-down resistances are supported. • Table 15 provides output driver characteristics for I/O pads when in SLOW configuration. • Table 16 provides output driver characteristics for I/O pads when in ...
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Electrical Characteristics Table 16. MEDIUM configuration output buffer electrical characteristics Symbol C Parameter Output high level OH MEDIUM configuration Output low level OL MEDIUM configuration 3.3 V ...
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Table 17. FAST configuration output buffer electrical characteristics (continued) Symbol C Parameter Output low level OL FAST configuration 3.3 V ± 10% / 5.0 V ± 10 ...
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Electrical Characteristics Table 18. Output pin transition times (continued) Symbol C Parameter Output transition time tr (4) output pin FAST configuration 3.3 V ± 10% / 5.0 V ± 10 ...
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Symbol C Parameter , Peak I/O current for SWTSLW SLOW configuration ( Peak I/O current for SWTMED MEDIUM configuration ( Peak I/O current for SWTFST FAST configuration Root ...
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Electrical Characteristics 4.7 RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. V DD_HV_A V DDMIN RESET device reset forced by RESET V RESET filtered by filtered by ...
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Table 21. Reset electrical characteristics (continued) Symbol C Parameter Input low Level CMOS IL (Schmitt Trigger Input hysteresis CMOS HYS (Schmitt Trigger Output low level Output transition ...
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Electrical Characteristics 4.8 Power management electrical characteristics 4.8.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply V supply V . The following supplies are involved: DD_HV_A • HV: High voltage ...
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ON. Apart from the bulk capacitance, user should connect EMI/decoupling cap ( each V REGP 4.8.1.1 Recommendations • The external NPN driver must be BCP68 type. • V should be ...
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Electrical Characteristics Table 22. Voltage regulator electrical characteristics (continued) Symbol — Low power regulator current LPREG provided Low power regulator module current LPREGINT consumption — Main LVDs and reference ...
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V DDHV/LV V LVDHVxH/LVxH V LVDHVxL/LVxL RESET Table 23. Low voltage monitor electrical characteristics Symbol Supply for functional POR module PORUP Power-on reset threshold PORH LVDHV3 low voltage detector high ...
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Electrical Characteristics Table 24. Low voltage power domain electrical characteristics Symbol C Parameter RUN mode maximum DDMAX average current RUN mode typical average DDRUN 8 current HALT mode ...
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Subject to change, Configuration: 1 e 1 DMA (10 ch.), 6 FlexCAN (4 Mbit/ Mbit/s), 16 1 RTC, 4 PIT channels, 1 SWT, 1 channels. RUN current measured with ...
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Electrical Characteristics Table 26 shows the data flash memory program and erase characteristics. Table 26. Data flash memory—Program and erase specifications Symbol C T Word (32 bits) program time wprogram block pre-program and erase time 16Kpperase ...
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ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Symbol ...
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Electrical Characteristics 4.10.3 Flash memory start-up/switch-off timings Symbol Delay for flash memory module to exit FLARSTEXIT reset mode Delay for flash memory module to exit FLALPEXIT low-power mode Delay for ...
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Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI measurements. Table 31. EMI radiated emission measurement Symbol ...
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Electrical Characteristics 4.11.3.2 Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: • A supply over-voltage is applied to each power supply pin. • A current injection is applied to each input, ...
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Nominal NDK crystal frequency reference (MHz) 4 NX8045GB 8 10 NX5032GA NX5032GA 1 The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the ...
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Electrical Characteristics Table 35. Fast external crystal oscillator ( MHz) electrical characteristics Symbol C Parameter Oscillation FXOSC amplitude at EXTAL Oscillation FXOSCOP operating point , Fast external crystal FXOSC ...
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OSC32K_EXTAL OSC32K_XTAL DEVICE Figure 12. Crystal oscillator and resonator connection scheme OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits. l Crystal C1 Figure 13. Equivalent circuit of a quartz crystal Symbol Parameter L Motional inductance m C Motional ...
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Electrical Characteristics 1 The crystal used is Epson Toyocom MC306. 2 This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3 ...
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FMPLL electrical characteristics The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Symbol C Parameter f SR — FMPLL reference clock PLLIN SR — FMPLL reference clock ...
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Electrical Characteristics Table 39. Fast internal RC oscillator (16 MHz) electrical characteristics Symbol C Parameter Fast internal RC oscillator high FIRCSTOP frequency and system clock current in stop mode Fast internal RC oscillator FIRCSU ...
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Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics (continued) Symbol C Slow internal RC oscillator precision SIRCPRE after software trimming of f Slow internal RC oscillator trimming SIRCTRIM step ...
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Electrical Characteristics 1023 1022 1021 1020 1019 1018 code out Offset Error OSE Figure 15. ADC_0 characteristic and error definitions 4.17.1.1 Input impedance and ADC accuracy To preserve the accuracy ...
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For instance, assuming a conversion rate of 1MHz, with CS+Cp (Reqiv = 1 / (fc*(CS+Cp )), where fc represents the conversion rate at the considered channel). To minimize the error induced 2 by the voltage partitioning between ...
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Electrical Characteristics In particular two different transient periods can be distinguished: • A first and quick charge transfer from the internal capacitance C is supposed initially completely discharged):considering a worst case (since the time constant in reality would be faster) ...
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Analog Source Bandwidth ( Anti-Aliasing Filter ( Figure 18. Spectral representation of input signal Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter according ...
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Electrical Characteristics 4.17.1.2 ADC electrical characteristics Symbol C Parameter Input leakage current T LKG Table 42. ADC conversion characteristics (10-bit ADC_0) Symbol C Parameter V SR — Voltage on SS_ADC0 VSS_HV_ADC0 (ADC_0 reference) pin ...
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Table 42. ADC conversion characteristics (10-bit ADC_0) (continued) Symbol C Parameter Internal resistance of SW2 analog source Internal resistance of AD analog source I SR — Input current Injection Current INJ | INL | ...
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Electrical Characteristics 4095 4094 4093 4092 4091 4090 code out Offset Error OSE Figure 19. ADC_1 characteristic and error definitions Table 43. Conversion characteristics (12-bit ADC_1) Symbol Parameter V ...
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Table 43. Conversion characteristics (12-bit ADC_1) (continued) Symbol Parameter Voltage on DD_ADC1 VDD_HV_ADC1 pin (ADC_1 reference) with respect to ground (V ) SS_HV 3 Analog input AINx 5 voltage f SR ADC_1 analog ADC1 frequency ...
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Electrical Characteristics Table 43. Conversion characteristics (12-bit ADC_1) (continued) Symbol Parameter I SR Input current INJ Injection INLP CC Absolute Integral non-linearity-Precis e channels INLS CC Absolute Integral non-linearity- Standard channels DNL CC Absolute Differential non-linearity OFS CC Absolute Offset ...
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Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. 4.18 Fast Ethernet Controller MII signals use CMOS signal levels compatible with devices ...
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Electrical Characteristics Spec Characteristic M5 TX_CLK to TXD[3:0], TX_EN, TX_ER invalid M6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid M7 TX_CLK pulse width high M8 TX_CLK pulse width low 1 Output pads configured with SRE = 0b11. TX_CLK (input) TXD[3:0] (outputs) ...
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Table 47. MII serial management channel timing Spec Characteristic M10 MDC falling edge to MDIO output invalid (minimum propagation delay) M11 MDC falling edge to MDIO output valid (max prop delay) M12 MDIO (input) to MDC rising edge setup M13 ...
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Electrical Characteristics 4.19 On-chip peripherals 4.19.1 Current consumption Table 48. On-chip peripherals current consumption Symbol C Parameter CAN DD_HV_A(CAN) (FlexCAN) supply current eMIOS supply DD_HV_A(eMIOS) current on V DD_HV_A ...
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Table 48. On-chip peripherals current consumption Symbol C Parameter IDD_HV_ADC1 CC D ADC_1 supply current on V DD_HV_ADC1 CFlash + DD_HV(FLASH) DFlash supply current on V DD_HV_ADC PLL supply DD_HV(PLL) current on V DD_HV ...
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Electrical Characteristics 4.19.2 DSPI characteristics Spec Characteristic 1 DSPI Cycle Time — Internal delay between pad associated to SCK and pad associated to CSn in master mode for CSn1->0 — Internal delay between pad associated to SCK and pad associated ...
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Spec Characteristic 9 Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) 10 Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE ...
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Electrical Characteristics CSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 24. DSPI classic SPI timing–master, CPHA = 0 CSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 25. DSPI ...
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SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) SOUT SIN Figure 26. DSPI classic SPI timing–slave, CPHA = 0 Freescale First Data Data Last Data 9 10 First Data ...
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Electrical Characteristics SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 5 SOUT SIN Figure 27. DSPI classic SPI timing–slave, CPHA = Last Data Data First Data 9 10 Data Last Data First Data ...
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CSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT First Data Figure 28. DSPI modified transfer format timing–master, CPHA = 0 Freescale First Data Last Data Data 12 11 Last Data ...
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Electrical Characteristics CSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 29. DSPI modified transfer format timing–master, CPHA = First Data Data 12 First Data Last Data Data Note: Numbers shown reference ...
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SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 5 SOUT SIN Figure 30. DSPI modified transfer format timing–slave, CPHA = 0 SS SCK Input (CPOL = 0) SCK Input (CPOL = SOUT SIN Figure ...
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Electrical Characteristics 7 PCSS CSx 4.19.3 Nexus characteristics Spec Characteristic 1 MCKO Cycle 2 Time 2 MCKO Duty Cycle 3 MCKO Low to MDO, MSEO, EVTO Data Valid 4 EVTI Pulse Width 5 EVTO Pulse Width 6 TCK Cycle Time ...
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MCKO MDO MSEO EVTO EVTI Freescale Figure 33. Nexus output timing MPC5646C Microcontroller DataSheet, Rev. 5.1 Electrical Characteristics Output Data Valid 5 95 ...
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Electrical Characteristics TCK TMS, TDI TDO 4.19.4 JTAG characteristics No. Symbol TCK cycle time JCYC TDI setup time TDIS TDI hold time TDIH ...
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No. Symbol TCK low to TDO valid TDOV TCK low to TDO invalid TDOI — TCK Duty Cycle TDC — TCK Rise and Fall Times ...
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Package characteristics 5 Package characteristics 5.1 Package mechanical data 5.1.1 176 LQFP package mechanical drawing 98 MPC5646C Microcontroller DataSheet, Rev. 5.1 Freescale ...
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Figure 36. 176 LQFP mechanical drawing (Part Freescale MPC5646C Microcontroller DataSheet, Rev. 5.1 Package characteristics 99 ...
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Package characteristics Figure 37. 176 LQFP mechanical drawing (Part 100 MPC5646C Microcontroller DataSheet, Rev. 5.1 Freescale ...
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Figure 38. 176 LQFP mechanical drawing (Part 5.1.2 208 LQFP package mechanical drawing Freescale MPC5646C Microcontroller DataSheet, Rev. 5.1 Package characteristics E E 101 ...
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Package characteristics Figure 39. 208 LQFP mechanical drawing (Part 102 MPC5646C Microcontroller DataSheet, Rev. 5.1 Freescale ...
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Figure 40. 208 LQFP mechanical drawing (Part Freescale MPC5646C Microcontroller DataSheet, Rev. 5.1 Package characteristics 103 ...
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Package characteristics Figure 41. 208 LQFP mechanical drawing (Part 104 MPC5646C Microcontroller DataSheet, Rev. 5.1 Freescale ...
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Freescale MPC5646C Microcontroller DataSheet, Rev. 5.1 Package characteristics 105 ...
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Package characteristics 5.1.3 256 MAPBGA package mechanical drawing Figure 42. 256 MAPBGA mechanical drawing (Part 106 MPC5646C Microcontroller DataSheet, Rev. 5.1 Freescale ...
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Figure 43. 256 MAPBGA mechanical drawing (Part Freescale MPC5646C Microcontroller DataSheet, Rev. 5.1 Package characteristics 107 ...
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Ordering information 6 Ordering information Example code: Automotive Platform Flash Size (core dependent) Fab and mask indicator R = Tape & Reel (blank if Tray) Qualification Status status S = Auto qualified status PC ...
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Revision history Table 52 summarizes revisions to this document. Revision Date 1 15 April 2010 Initial Release 2 17 Aug 2010 Freescale Table 52. Revision history Changes • Editing and formatting updates throughout the document. • Updated Voltage regulator ...
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Revision history Revision Date 3 28 April 2011 110 Table 52. Revision history (continued) Changes • Replaced VIL min from –0 –0 the following tables: - I/O input DC electrical characteristics - Reset electrical characteristics - ...
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Revision Date 4 23 June 2011 Freescale Table 52. Revision history (continued) Changes • Interchanged the denominator with numerator in Equation 11 of Input impedance and ADC accuracy section • Removed the note (All ADC conversion characteristics described in the ...
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Revision history Revision Date 5 21 June 2012 5.1 15 Aug 2012 This revision history uses clickable cross-references for ease of navigation. The numbers and titles in each cross-reference are relative to the latest published release. 112 Table 52. Revision ...
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Appendix A Abbreviations Table 53 lists abbreviations used but not defined elsewhere in this document. Abbreviation CS EVTO MCKO MDO MSEO MTFE SCK SOUT TBD TCK TDI TDO TMS Freescale Table 53. Abbreviations Meaning Chip select Event out Message clock ...
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Abbreviations 114 MPC5646C Microcontroller DataSheet, Rev. 5.1 Freescale ...
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