MAX1279BCTC-T Maxim Integrated, MAX1279BCTC-T Datasheet - Page 10

• Manufacturer Part Number: MAX1279BCTC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1279BCTC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.5 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: 68.5 dB
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1277/MAX1279, which is composed
of a T/H, a comparator, and a switched-capacitor digi-
tal-to-analog converter (DAC). The T/H enters its track-
ing mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is con-
nected to AIN+. The negative input capacitor is con-
nected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is convert-
ed. The time required for the T/H to acquire an input sig-
nal is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens. The acquisition time,
t
acquired. It is calculated by the following equation:
where R
the input signal.
Note: t
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
The ADC’s input-tracking circuitry has a 15MHz small-
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Figure 5. Interface-Timing Sequence
Figure 6. SPI Interface—Partial Power-Down Mode
10
ACQ
, is the minimum time needed for the signal to be
______________________________________________________________________________________
ACQ
IN
= 200Ω, and RS is the source impedance of
CNVST
True-Differential Analog Input T/H
DOUT
is never less than 125ns and any source
SCLK
CNVST
MODE
t
DOUT
SCLK
ACQ
HIGH IMPEDANCE
REF
≥ 9 × (RS + R
t
SETUP
0
1ST SCLK RISING EDGE
1
0
IN
2
) × 16pF
Input Bandwidth
0
ONE 8-BIT TRANSFER
NORMAL
3
D11
4
D11
D10
D10
D9
POWER-MODE SELECTION WINDOW
D9
ENABLED (2.048V)
D8
D8
8
D7
D7
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Internal protection diodes that clamp the analog input
to V
from GND - 0.3V to V
inputs must not exceed V
accurate conversions.
Upon initial power-up, the MAX1277/MAX1279 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a conver-
sion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
D6
DD
D5
and GND allow the analog input pins to swing
D4
D3
PPD
D2
14
Initialization After Power-Up
D1
DD
and Starting a Conversion
t
Analog Input Protection
ACQUIRE
D0
+ 0.3V without damage. Both
DD
16
CONTINUOUS-CONVERSION
SELECTION WINDOW
or be lower than GND for
Serial Interface