MAX1279BCTC-T Maxim Integrated, MAX1279BCTC-T Datasheet - Page 12

• Manufacturer Part Number: MAX1279BCTC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1279BCTC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.5 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: 68.5 dB
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Figure 8. Unipolar Transfer Function (MAX1277 Only)
Figure 9. Bipolar Transfer Function (MAX1279 Only)
12
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
111...111
111...110
111...101
000...011
000...010
000...001
000...000
OUTPUT CODE
OUTPUT CODE
______________________________________________________________________________________
0
-FS
1
2
1 LSB =
- FS =
FS =
ZS = 0
3
V
4096
V
-V
REF
REF
2
2
REF
DIFFERENTIAL INPUT
DIFFERENTIAL INPUT
VOLTAGE (LSB)
VOLTAGE (LSB)
0
FULL-SCALE
TRANSITION
FULL-SCALE
TRANSITION
FS - 3/2 LSB
FS - 3/2 LSB
1 LSB =
FS = V
ZS = 0
FS
4096
V
REF
REF
FS
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out on
DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CNVST or SCLK, enabling
the serial interface to be shared by multiple devices. If
CNVST returns high after the 14th, but before the 16th
SCLK rising edge, DOUT remains active so continuous
conversions can be sustained. The highest throughput is
achieved when performing continuous conversions. Figure
10 illustrates a conversion using a typical serial interface.
The MAX1277/MAX1279 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 24MHz.
When using SPI or MICROWIRE, the MAX1277/ MAX1279
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
12 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid t
remains valid until t
edge. When using CPOL = 0 and CPHA = 0, or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the fol-
lowing rising edge. When using CPOL = 0 and CPHA = 1,
or CPOL = 1 and CPHA = 0, the data is clocked into the
µP on the next falling edge. See
and Figures 12 and 13 for timing. See the Timing
Characteristics section to determine the best mode to use.
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1277/MAX1279 require 16 clock cycles
from the µP to clock out the 12 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
12 data bits, and a trailing zero with the data in MSB-
DHOLD
How to Start a Conversion
Standard Interfaces
after the following SCLK rising
SPI and MICROWIRE
Figure
Connection to
11 for connections
DOUT
later and
QSPI