MAX1279BCTC-T Maxim Integrated, MAX1279BCTC-T Datasheet - Page 11

• Manufacturer Part Number: MAX1279BCTC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1279BCTC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.5 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: 68.5 dB
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serial-
interface operation.
A CNVST falling edge initiates a conversion sequence;
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the conver-
sion is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t
SCLK’s rising edge and remains valid 4ns (t
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CNVST high between the
14th and the 16th SCLK rising edges. If CNVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CNVST’s rising edge or the next SCLK’s rising edge.
Power consumption can be reduced significantly by plac-
ing the MAX1277/MAX1279 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 2mA. While in par-
tial power-down mode, the reference remains enabled to
allow valid conversions once the IC is returned to normal
mode. Drive CNVST low and allow at least 14 SCLK
cycles to elapse before driving CNVST high to exit partial
power-down mode.
Figure 7. SPI Interface—Full Power-Down Mode
Differential, 12-Bit ADCs with Internal Reference
MODE
CNVST
DOUT
REF
SCLK
______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, True-
Partial Power-Down and
Full Power-Down Modes
1ST SCLK RISING EDGE
0
0
Timing and Control
0
NORMAL
FIRST 8-BIT TRANSFER
D11
DOUT
D10
after each
D9
DHOLD
1ST SCLK RISING EDGE
D8
)
D7
ENABLED (2.048V)
PPD
Full power-down mode is ideal for infrequent data sam-
pling and very low supply current applications. The
MAX1277/MAX1279 have to be in partial power-down
mode to enter full power-down mode. Perform the
SCLK/CNVST sequence described above to enter par-
tial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. While in full power-down mode, the refer-
ence is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
power-down mode for the reference to settle. In
partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.
Figure 8 shows the unipolar transfer function for the
MAX1277. Figure 9 shows the bipolar transfer function for
the MAX1279. The MAX1277 output is straight binary,
while the MAX1279 output is two’s complement.
The MAX1277/MAX1279 have an on-chip voltage refer-
ence trimmed to 2.048V. The internal reference output
is connected to REF and also drives the internal capac-
itive DAC. The output can be used as a reference volt-
age source for other components and can source up to
2mA. Bypass REF with a 0.01µF capacitor and a 4.7µF
capacitor to RGND.
The internal reference is continuously powered up dur-
ing both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Be sure to allow at least 2ms recovery time after hard-
ware power-up or exiting full power-down mode for the
reference to reach its intended value.
0
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
0
EXECUTE PARTIAL POWER-DOWN TWICE
0
SECOND 8-BIT TRANSFER
RECOVERY
Applications Information
0
0
0
0
Internal Reference
Transfer Function
0
DISABLED
FPD
11