MAX1279BCTC-T Maxim Integrated, MAX1279BCTC-T Datasheet - Page 16

• Manufacturer Part Number: MAX1279BCTC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1279BCTC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.5 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: 68.5 dB
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
Figure 20. Power-Supply Grounding Condition
16
Figure 19. Interfacing to the ADSP21_ _ _
______________________________________________________________________________________
V
CNVST
DD
DOUT
SCLK
MAX1277
MAX1279
0.1μF
10μF
MAX1277
MAX1279
CNVST
DOUT
SCLK
GND RGND
1
V
0
L
GND
0
SUPPLIES
0.1μF
10μF
0
D11
V
L
VDDINT
TCLK
RCLK
TFS
RFS
DR
D10
ADSP21_ _ _
D9
CIRCUITRY
DGND
DIGITAL
D8
V
V
D7
L
L
D6
D5
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the V
when the MAX1277/MAX1279 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the V
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1277/MAX1279 are mea-
sured using the end-points method.
D4
D3
Layout, Grounding, and Bypassing
D2
L
D1
pin to the ADSP21_ _ _ supply voltage
D0
0
Integral Nonlinearity
DD
power supply can
Definitions
1
0
0