MK40DN512VLQ10 Freescale Semiconductor, MK40DN512VLQ10 Datasheet
MK40DN512VLQ10
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MK40DN512VLQ10 Summary of contents
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... External watchdog monitor – Software watchdog – Low-leakage wakeup unit Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2011–2013 Freescale Semiconductor, Inc. Document Number: K40P144M100SF2 Rev. 7, 02/2013 K40P144M100SF2 • Security and integrity modules – ...
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... USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – I2S module K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 2 Freescale Semiconductor, Inc. ...
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... Switching specifications.....................................................21 5.3.1 Device clock specifications.................................21 5.3.2 General switching specifications.........................21 5.4 Thermal specifications.......................................................22 5.4.1 Thermal operating requirements.........................22 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Table of Contents 5.4.2 Thermal attributes...............................................23 6 Peripheral operating requirements and behaviors....................24 6.1 Core modules....................................................................24 6.1.1 Debug trace timing specifications.......................24 6.1.2 JTAG electricals..................................................25 6 ...
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... Pinout........................................................................................67 8.1 K40 Signal Multiplexing and Pin Assignments..................67 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 4 8.2 K40 Pinouts.......................................................................73 9 Revision History........................................................................75 Freescale Semiconductor, Inc. ...
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... Qualification status K## Kinetis family A Key attribute M Flash memory type K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. freescale.com and perform a part number search for the Description • Fully qualified, general market flow • Prequalification • K40 • Cortex-M4 w/ DSP • ...
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... LQ = 144 LQFP ( mm) • 144 MAPBGA ( mm) • 256 MAPBGA ( mm) • MHz • MHz • 100 MHz • 120 MHz • 150 MHz • Tape and reel • (Blank) = Trays Values Freescale Semiconductor, Inc. ...
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... An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. Max. 0.9 1.1 Min. Max. 10 130 Min. ...
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... Result of exceeding a rating Measured characteristic K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 8 Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Max. Unit V Freescale Semiconductor, Inc. ...
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... Typical values are provided as design guidelines and are neither tested nor guaranteed. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Normal operating range Degraded operating range - No permanent failure ...
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... Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply voltage DD K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 10 Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Max. Unit 130 µ 150 °C 105 °C 25 °C –40 °C Unit °C V Freescale Semiconductor, Inc. ...
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... Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.4 Voltage and current operating ratings K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. Max. Unit –55 150 ° ...
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... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 12 Min. Max. Unit –0.3 3.8 V — 185 mA –0.3 5.5 V –0 0 – – –0.3 3.63 V –0.3 3.63 V –0.3 6.0 V –0.3 3.8 V Freescale Semiconductor, Inc. ...
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... The positive injection current limiting resistor is calculated as R=(V AIO_MIN IN ICAIO larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. 1.71 1.71 –0.1 –0.1 1.71 0.7 × ...
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... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 14 supply LVD and POR operating requirements Min. 0.8 2.48 2.62 2.72 2.82 2.92 — 1.54 1.74 1.84 1.94 2.04 — 0.97 900 Min. 0.8 Typ. Max. Unit Notes 1.1 1.5 V 2.56 2.64 V 2.70 2.78 V 2.80 2.88 V 2.90 2.98 V 3.00 3.08 V ±80 — mV 1.60 1.66 V 1.80 1.86 V 1.90 1.96 V 2.00 2.06 V 2.10 2.16 V ±60 — mV 1.00 1.03 V 1000 1100 μs Typ. Max. Unit Notes 1.1 1.5 V Freescale Semiconductor, Inc ...
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... Input leakage current, digital pins IND • V < V < • 3 • 3 • 2 • 1 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. = -9mA V – 0 -3mA V – 0 -2mA V – 0 -0.6mA V – 0 — ...
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... DD SS min and Vinput = Digital input , and VLLSx→RUN recovery times in the following table 1 Typ. Max. Unit Notes μA 4, — 48 kΩ — 55 kΩ — 57 kΩ — 85 kΩ kΩ kΩ Freescale Semiconductor, Inc ...
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... Wait mode reduced frequency current at 3.0 V — DD_WAIT all peripheral clocks disabled I Very-low-power run mode current at 3.0 V — all DD_VLPR peripheral clocks disabled K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. DD — — — — — — ...
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... Table continues on the next page... Max. Unit Notes — — 1.4 mA 7.9 mA 19.2 mA 435 μA 2000 μA 4000 μ μA 68 μA 270 μA 9 8.9 μA 35 μA 148 μA 5.4 μA 12.5 μA 125 μA 7.6 μA 13.5 μA 46 μA 0.39 μA 0.78 μA 2.9 μA Freescale Semiconductor, Inc. ...
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... USB regulator disabled • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. Typ. Max. Unit — ...
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... Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 0.15–1000 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 144LQFP 144MAPBGA Unit 23 12 dBμ dBμ dBμ dBμ — Freescale Semiconductor, Inc. Notes ...
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... SYS_USB operation f Bus clock BUS FB_CLK FlexBus clock f Flash clock FLASH f LPTMR clock LPTMR K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc MHz 48MHz SYS BUS Table 8. Capacitance attributes Min. Normal run mode — 20 — — — — ...
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... Min. Max. Unit 1.5 — Bus clock cycles 100 — — ns 100 — — Bus clock cycles — — — — — — — — Freescale Semiconductor, Inc. Notes ...
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... Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. –40 –40 ...
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... T Data hold h Figure 3. TRACE_CLKOUT specifications TRACE_CLKOUT TRACE_D[3:0] Figure 4. Trace data specifications K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 24 Min. Frequency dependent 2 2 — — Max. Unit MHz — ns — — ns — Freescale Semiconductor, Inc. ...
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... TCLK frequency of operation • Boundary Scan • JTAG and CJTAG • Serial Wire Debug J2 TCLK cycle period K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table continues on the next page... Min. Max. Unit 2.7 3 ...
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... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013 Figure 5. Test clock input timing Min. Max. Unit 50 — — ns 12.5 — ns — — — ns — — — ns 1.4 — ns — 22.1 ns — 22.1 ns 100 — — Freescale Semiconductor, Inc. ...
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... Data outputs Data outputs Data outputs Figure 6. Boundary scan (JTAG) timing TCLK TDI/TMS TDO TDO TDO K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J11 J12 J11 Figure 7. Test Access Port timing J5 ...
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... FLL 31.25 Table continues on the next page... Max. Unit Notes — kHz — 38.2 kHz ± 0 dco ± 4 dco 4 — MHz — 5 MHz — — kHz — — kHz — 39.0625 kHz Freescale Semiconductor, Inc. ...
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... MHz vco D Lock entry frequency tolerance lock D Lock exit frequency tolerance unl t Lock detector detection time pll_lock K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 20 20.97 640 × f fll_ref 40 41.94 1280 × f fll_ref 60 62.91 1920 × ...
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... Table continues on the next page... Max. Unit Notes 3 — nA — μA — μA — μA — mA — — μA — μA — μA — mA — mA — mA — — Freescale Semiconductor, Inc. ...
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... Oscillator crystal or resonator frequency — low osc_lo frequency mode (MCG_C2[RANGE]=00) f Oscillator crystal or resonator frequency — high osc_hi_1 frequency mode (low range) (MCG_C2[RANGE]=01) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — — — — ...
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... Max. 8 — 32 — — — 750 — — 250 — — 0.6 — — 1 — NOTE Min. Typ. 1.71 — — 100 — 5 — 0.6 Freescale Semiconductor, Inc. Unit Notes MHz MHz Max. Unit 3.6 V — MΩ — V ...
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... Read 1s Block execution time t • 256 KB program/data flash rd1blk256k t Read 1s Section execution time (flash sector) rd1sec2k K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — 700 and V specifications do not apply. The voltage of the applied ...
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... Freescale Semiconductor, Inc ...
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... Data retention after cycles nvmretp1k n Cycling endurance nvmcycp t Data retention after cycles nvmretd10k K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 175 — 385 — 475 — ...
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... EEESPLIT × EEESIZE 1 Typ. Max. Unit Notes 100 — years 50 K — cycles 50 — years 100 — years 175 K — writes 1.6 M — writes 6.4 M — writes 50 M — writes 400 M — writes ≤ 125°C. j × Write_efficiency × n nvmcycd Freescale Semiconductor, Inc ...
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... Figure 9. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 24. EzPort switching specifications Num Description Operating voltage K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table continues on the next page... Min. Max. Unit 1.71 3.6 ...
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... EP3 EP2 EP4 EP9 EP8 EP7 EP5 EP6 Figure 10. EzPort Timing Diagram Min. Max. Unit — MHz SYS — MHz SYS — ns EZP_CK 5 — — — — ns — — ns — Freescale Semiconductor, Inc. ...
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... Data and FB_TA input hold 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. Unit 2 ...
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... Peripheral operating requirements and behaviors FB1 FB_CLK FB_A[Y] FB2 FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 11. FlexBus read timing diagram K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 40 FB3 FB5 Address FB4 Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ Freescale Semiconductor, Inc. ...
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... FB_TSIZ[1:0] Figure 12. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB3 Address Data AA=1 ...
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... Table 29 and 1 Max. Unit Notes — 3 +100 +100 DDA DDA V V SSA SSA — 31/ VREFH — VREFH kΩ 3 — 5 kΩ — 18.0 MHz 4 — 12.0 MHz 4 5 — 818.330 Ksps Freescale Semiconductor, Inc. ...
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... Table 28. 16-bit ADC characteristics (V Symbol Description Conditions I Supply current DDA_ADC K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 37.037 — = 1.0 MHz, unless otherwise stated. Typical values are for ADCK ADC calculator ...
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... Notes 3 MHz ADACK f ADACK 6.1 MHz 7.3 MHz 9.5 MHz 4 ±6.8 LSB 5 ±2.1 4 -1.1 to +1.9 LSB 5 -0.3 to 0.5 4 -2.7 to +1.9 LSB 5 -0.7 to +0.5 4 -5.4 LSB V = ADIN V DDA -1 — LSB ±0.5 6 — bits — bits — bits — bits dB 7 — dB — — dB — dB Freescale Semiconductor, Inc. ...
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... Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = ...
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... VREF_OU VREF_OU VREF_OU — SSA V — SSA — 128 — 64 — 32 — 100 1.25 — Table continues on the next page... Max. Unit Notes 3 DDA V V DDA 4 — kΩ IN+ to IN- — — — Ω 5 — µs 6 Freescale Semiconductor, Inc. ...
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... Input DC current DC_PGA Gain = =0.5V CM Gain =64 =0.1V CM K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 Min. Typ. 18.484 — 37.037 — MHz unless otherwise stated. Typical values are for ADCK PGAD Min ...
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... OFS 10 µ leakage AS In current (refer to the MCU's voltage and current operating ratings × 0.583 — dB 16-bit differential — dB mode, Average=32 — dB 16-bit differential — dB mode, Average=32, f =100Hz in — dB 16-bit differential — dB mode, Average=32, f =100Hz in Freescale Semiconductor, Inc. ...
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... Analog comparator hysteresis H • CR0[HYSTCTR • CR0[HYSTCTR • CR0[HYSTCTR • CR0[HYSTCTR Output high CMPOh V Output low CMPOl t Propagation delay, high-speed mode (EN=1, DHS PMODE=1) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 11.6 13.4 7.2 9.6 12.8 14.5 11.0 14.3 7.9 13.8 7.3 13.1 6.8 12 ...
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... Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 50 Min — — –0.5 –0.3 -0 1.3 1.6 1.9 2.2 Vin level (V) Typ. Max. Unit 250 600 ns — 40 μs 7 — μA 3 — 0.5 LSB — 0.3 LSB HYSTCTR S etting 2.5 2.8 3.1 Freescale Semiconductor, Inc. ...
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... L I Output load current L 1. The DAC reference can be selected small load capacitance (47 pF) can improve the bandwidth performance of the DAC K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1.3 1.6 1.9 2.2 Vin level (V) Min ...
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... Notes 150 μA 700 μA 200 μ μ μs 1 100 DACR ±8 LSB 2 ±1 LSB 3 ±1 LSB 4 ±0.8 %FSR 5 ±0.6 %FSR — μV/C 6 — %FSR/C 250 Ω V/μs — — -80 dB kHz — — Freescale Semiconductor, Inc. ...
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... Figure 18. Typical INL error vs. digital code K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 53 ...
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... The load capacitance should not exceed +/-25% of the nominal specified C the device. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 54 Min. Max. Unit 1.71 3.6 V Operating temperature °C range of the device 100 nF value over the operating temperature range of L Freescale Semiconductor, Inc. Notes 1, 2 ...
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... Symbol Description V Voltage reference output with factory trim out 6.7 Timers See General switching specifications. 6.8 Communication interfaces K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. Max. 1.1915 1.195 1.1977 1.1584 — 1.2376 — ...
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... Table continues on the next page... Typ. Max. Unit — 0.7 V — 2 μA 100 150 μA — 24.8 kΩ 0.33 0 Max. Unit Notes 5.5 V 186 μA 30 μA — μA 120 3.6 V 3 8.16 μF 100 mΩ Freescale Semiconductor, Inc. ...
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... DSPI_SIN to DSPI_SCK input setup DS8 DSPI_SCK to DSPI_SIN input hold 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 Min. Typ. Max. Unit — ...
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... First data Data DS14 First data Data DS4 Min. Max. Unit 2.7 3.6 V 12.5 MHz — ns BUS (t /2) − / SCK SCK — — — — ns — — DS9 DS16 DS11 Last data Last data Freescale Semiconductor, Inc. ...
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... Figure 22. DSPI classic SPI timing — master mode Table 43. Slave mode DSPI timing (full voltage range) Num Operating voltage Frequency of operation K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1.71 — BUS ...
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... DS9 DS16 DS11 Last data Last data Fast Mode Unit Minimum Maximum 0 400 kHz 0.6 — 1.3 — 0.6 — 0.6 — 0 100 — +0.1C 300 b Freescale Semiconductor, Inc. µs µs µs µs µ ...
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... HD; DAT Figure 24. Timing definition for fast and standard mode devices on the I 6.8.8 UART switching specifications See General switching specifications. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2 Table 44 timing (continued) Symbol Standard Mode ...
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... K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 62 Card input clock SD3 SD2 SD1 SD6 SD7 SD8 Figure 25. SDHC timing Min. Max. Unit 0 400 kHz 0 25\50 MHz 0 20\50 MHz 0 400 kHz 7 — — ns — — 8 — — ns Freescale Semiconductor, Inc. ...
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... I2S_BCLK (output I2S_FS (output) I2S_FS (input) S7 I2S_TXD I2S_RXD Figure 26. I K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors master (clocks driven) and slave S master mode timing (limited voltage range ...
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... MCLK period 10 — — ns — — — — ns S16 S14 S16 Min. Max. Unit 1.71 3 SYS 45% 55% MCLK period — ns SYS 45% 55% BCLK period — -4.3 — ns — -4.6 — ns 23.9 — — ns Freescale Semiconductor, Inc. ...
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... The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2 S slave mode timing (full voltage range) Min ...
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... Table continues on the next page... ref = 1.0 pF. The ref = 32 μA, REFCHRG = 31 0.5 ref ref Max. Unit Notes 58 Hz — — 8000 — V — V — V — V — V — IREG — µA 4 — µA — µA Freescale Semiconductor, Inc. ...
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... Package dimensions are provided in package drawings. To find a package drawing drawing’s document number: If you want the drawing for this package 144-pin LQFP 144-pin MAPBGA 8 Pinout K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. Min. Typ. — 0.28 — 2.98 2.0 − 5% 2.0 3.3 − ...
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... PTE9 UART5_RX I2S0_RX_ BCLK PTE10 UART5_CTS_ I2S0_TXD b PTE11 UART5_RTS_ I2S0_TX_FS b PTE12 I2S0_TX_ BCLK ALT5 ALT6 ALT7 EzPort FB_AD27 I2C1_SDA FB_AD26 I2C1_SCL FB_AD24 FB_CS3_b/ FB_TA_b FB_BE7_0_b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_b FB_ALE/ I2S0_CLKIN FB_CS1_b/ FB_TS_b FB_CS0_b FB_AD4 FB_AD3 FB_AD2 FB_AD1 FB_AD0 Freescale Semiconductor, Inc. ...
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... ADC0_SE17 46 K5 PTE25 ADC0_SE18 ADC0_SE18 47 K4 PTE26 DISABLED 48 J4 PTE27 DISABLED 49 H4 PTE28 DISABLED K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTE24 CAN1_TX UART4_TX PTE25 CAN1_RX UART4_RX PTE26 UART4_CTS_ b PTE27 UART4_RTS_ b PTE28 Pinout ...
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... FB_AD17 FTM1_QD_ TRACE_D2 PHA FB_AD16 FTM1_QD_ TRACE_D1 PHB FB_AD15 FTM2_QD_ TRACE_D0 PHA FB_OE_b FTM2_QD_ PHB FB_CS5_b/ I2S0_TXD FTM1_QD_ FB_TSIZ1/ PHA FB_BE23_16_ b FB_CS4_b/ I2S0_TX_FS FTM1_QD_ FB_TSIZ0/ PHB FB_BE31_24_ b FB_AD31 I2S0_TX_ BCLK FB_AD30 I2S0_RXD FB_AD29 I2S0_RX_FS FB_AD28 I2S0_MCLK I2S0_CLKIN LPT0_ALT1 Freescale Semiconductor, Inc. ...
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... D12 PTB18 LCD_P14/ LCD_P14/ TSI0_CH11 TSI0_CH11 98 D11 PTB19 LCD_P15/ LCD_P15/ TSI0_CH12 TSI0_CH12 99 D10 PTB20 LCD_P16 LCD_P16 K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA24 PTA25 PTA26 PTA27 PTA28 PTA29 PTB0/ I2C0_SCL FTM1_CH0 LLWU_P5 PTB1 ...
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... I2S0_RXD LLWU_P11 PTC12 UART4_RTS_ b PTC13 UART4_CTS_ b PTC14 UART4_RX PTC15 UART4_TX ALT5 ALT6 ALT7 EzPort CMP1_OUT LCD_P17 CMP2_OUT LCD_P18 LCD_P19 LCD_P20 LCD_P21 LCD_P22 LCD_P23 CMP1_OUT LCD_P24 CMP0_OUT LCD_P25 LCD_P26 LCD_P27 LCD_P28 FTM2_FLT0 LCD_P29 LCD_P30 LCD_P31 LCD_P32 LCD_P33 LCD_P34 LCD_P35 Freescale Semiconductor, Inc. ...
Page 73
... The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ...
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... PTB22 PTB21 100 99 PTB20 PTB19 98 97 PTB18 PTB17 96 95 PTB16 VDD 94 93 VSS PTB11 92 91 PTB10 PTB9 90 PTB8 89 PTB7 88 PTB6 87 PTB5 86 PTB4 85 PTB3 84 PTB2 83 82 PTB1 PTB0 81 80 PTA29 PTA28 79 78 PTA27 PTA26 77 76 PTA25 PTA24 75 RESET_b 74 PTA19 73 Freescale Semiconductor, Inc. ...
Page 75
... Figure 29. K40 144 MAPBGA Pinout Diagram 9 Revision History The following table provides a revision history for this document. Rev. No. Date Substantial Changes 1 11/2010 Initial public revision K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc PTC8 PTD0 PTC16 PTC12 ...
Page 76
... Added LCD glass capacitance footnote K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 76 footnote in "Voltage and Current Operating Requirements" table. IC spec in "Power consumption operating behaviors" table DD_VBAT description and specs in "USB VREG electrical specifications" table LIM Table continues on the next page... Freescale Semiconductor, Inc. ...
Page 77
... In "SDHC specifications", removed the operating voltage limits and updated the SD1 and SD6 specs. • In "I2S switching specifications", added separate specification tables for the full operating voltage range. K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc. numbers in 'Power consumption operating behaviors' section. DD_RUN . LAT ...
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... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...