W65C02S6TQG-14 Western Design Center (WDC), W65C02S6TQG-14 Datasheet - Page 30

• Manufacturer Part Number: W65C02S6TQG-14
• Description: Microprocessors - MPU 8-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C02S6TQG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-44
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 15

Indexed addressing across page
boundary
Execution of invalid OpCodes.
Jump indirect, operand = XXFF.
Read/Modify/Write
effective address.
Decimal flag.
Flags after decimal operation.
Interrupt
instruction
Ready.
Read/Modify/Write
absolute indexed in same page.
Oscillator.
Assertion of Ready (RDY) during
write operations.
Clock inputs.
Unused input-only pins and RDY.
7
The BRK instruction for both the NMOS 6502 and 65C02 is a 2 byte instruction. The NMOS and CMOS
devices simply skips the second byte (i.e. doesn’t care about the second byte) by incrementing the
program counter twice. It is important to realize that if a return from interrupt is used it will return to the
location after the second or signature byte.
CAVEATS
after
Function
fetch
instruction
Table 7-1 Microprocessor Operational Enhancements
instructions
of
BRK
at
Extra read of invalid address.
Some
Results are undefined.
One read and two write cycles.
Indeterminate after reset.
Invalid N, V and Z flags.
Interrupt vector is loaded; BRK vector
is ignored.
Input.
Seven cycles.
Requires
components.
Ignored.
PHI2 is the only required clock.
Page address does not increment.
Must be tied to VDD.
terminate
NMOS 6502
external
only
by
active
reset.
Extra read of last instruction byte.
All are NOP's (reserved for future use).
02,22,42,62,82
C2, E2
X3,OB-BB,EB,FB
44
54,D4,F4
5C
DC,FC
Page address increments, one additional
cycle.
Two read and one write cycle.
Initialized to binary mode (D=0) after reset
and interrupts.
Valid flags. One additional cycle.
BRK is executed, and then interrupt is
executed.
Bi-directional, WAI instruction pulls low.
Latest TSMC devices no longer have an
internal pull up. An external pullup should
be used if RDY is not driven and a resistor
added when driven by a gate to allow for
the W65C02S to pull RDY low.
Six cycles.
Crystal or RC network will oscillate when
connected between PHI2 and PHI10.
Stops processor during PHI2, and WAI
instruction pulls RDY low.
PHI2 is the only required clock.
Must be tied to VDD.
OpCode
W65C02S
Bytes
2
1 1
2
2
3
3
Cycles
2
30
3
4
8
4