W65C02S6TQG-14 Western Design Center (WDC), W65C02S6TQG-14 Datasheet - Page 6

• Manufacturer Part Number: W65C02S6TQG-14
• Description: Microprocessors - MPU 8-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C02S6TQG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-44
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 15

The internal organization of the W65C02S is divided into two parts: 1) Register Section and 2) Control
Section. Instructions obtained from program memory are executed by implementing a series of data
transfers within the Register Section. Signals that cause data transfers are generated within the Control
Section.
2.1
The Operation Code (OpCode) portion of the instruction is loaded into the Instruction Register from the Data
Bus and is latched during the OpCode fetch cycle. The OpCode is then decoded, along with timing and
interrupt signals, to generate various control signals for program execution.
2.2
The Timing Control Unit (TCU) provides timing for each instruction cycle that is executed. The TCU is set
to zero for each instruction fetch, and is advanced at the beginning of each cycle for as many cycles as is
required to complete the instruction. Data transfers between registers depend upon decoding the
contents of both the IR and the TCU.
2.3
All arithmetic and logic operations take place within the ALU. In addition to data operations, the ALU also
calculates the effective address for relative and indexed addressing modes. The result of a data operation
is stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags are updated
following the ALU data operation.
2.4
The Accumulator Register (A) is an 8-bit general purpose register which holds one of the operands and the
result of arithmetic and logical operations. Reconfigured versions of this processor family could have
additional accumulator
2.5
There are two 8-bit Index Registers (X and Y) which may be used as general purpose registers or to provide
an index value for calculation of the effective address.
addressing, the microprocessor fetches the OpCode and the base address, and then modifies the address
by adding the Index Register contents to the address prior to performing the desired operation
2.6
The 8-bit Processor Status Register (P) contains status flags and mode select bits. The Carry (C),
Negative (N), Overflow (V) and Zero (Z) status flags serve to report the status of ALU operations. These
status flags are tested with Conditional Branch instructions. The Decimal (D) and IRQB disable (I) are
used as mode select flags. These flags are set by the program to change microprocessor operations. Bit
5 is available for a user status or mode bit.
2 FUNCTIONAL DESCRIPTION
Instruction Register (IR) and Decode
Timing Control Unit (TCU)
Arithmetic and Logic Unit (ALU)
Accumulator Register (A)
Index Registers (X and Y)
Processor Status Register (P)
s.
When executing an instruction with indexed
.
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