554PC000523DG Silicon Labs, 554PC000523DG Datasheet
554PC000523DG
Specifications of 554PC000523DG
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554PC000523DG Summary of contents
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Q F UAD SCILLATOR Features Available with any-rate output frequencies from 10–945 MHz and selected frequencies to 1.4 GHz Four ...
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Si 554 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current Output Enable (OE) 2 and Frequency Select FS[1:0] Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" ...
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Table 3. CLK± Output Frequency Characteristics Parameter Symbol 1,2,3 Nominal Frequency 1,4 Temperature Stability 1,4 Absolute Pull Range APR Aging 5 Power up Time t Settling Time After FS[1:0] t Change Notes: 1. See Section 3. "Ordering Information" on page ...
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Si 554 Table 5. CLK± Output Phase Jitter Parameter Symbol 1,2,3 Phase Jitter (RMS) for F > 500 MHz OUT Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always ...
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Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,3,4,5 Phase Jitter (RMS) for F of 125 to 500 MHz OUT Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, ...
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Si 554 Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,5 Phase Jitter (RMS) for 160 MHz OUT CMOS Output Only Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter ...
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Table 7. CLK± Output Phase Noise (Typical) Offset Frequency 74.25 MHz 90 ppm/V LVPECL 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Table 8. Environmental Compliance The Si554 meets the following qualification test requirements. ...
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Si 554 2. Pin Descriptions Pin Name OE* 3 GND 4 CLK+ CLK– 5 (N/A for CMOS FS[1]* 8 FS[0]* *Note: FS[1:0] and OE include a 17 k pullup resistor to V ...
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... Specific device configurations are programmed into the Si554 at time of shipment. Configurations are DD specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to and for further ordering instructions. The Si554 VCXO series is supplied in an industry-standard, RoHS-compliant, lead-free, 8-pad package ...
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Si 554 4. Package Outline and Suggested Pad Layout Figure 2 illustrates the package details for the Si554. Table 11 lists the values for the dimensions shown in the illustration. Table 11. Package Diagram Dimensions (mm) Dimension A b ...
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PCB Land Pattern Figure 3 illustrates the 8-pin PCB land pattern for the Si554. Table 12 lists the values for the dimensions shown in the illustration. Table 12. PCB Land Pattern Dimensions (mm) Dimension ...
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Si 554 6. Top Marking 6.1. Si554 Top Marking 6.2. Top Marking Explanation Line Position 1 1–10 “SiLabs”+ Part Family Number, 554 (First 3 characters in part number) 2 1–10 Si554: Option1+Option2+Freq(7)+Temp Si554 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp 3 Trace ...
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OCUMENT HANGE IST Revision 0.6 to Revision 1.0 Updated Table 4 on page 3. Updated 2.5 V/3.3 V and 1.8 V CML output level specifications. Updated Table 5 on page 4. Removed the words ...
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