M95512-DFCS6TP/K STMicroelectronics, M95512-DFCS6TP/K Datasheet - Page 15

• Manufacturer Part Number: M95512-DFCS6TP/K
• Description: EEPROM 512Kb Serial Bus 2.5V to 5.5V 10MHz
• Manufacturer: STMicroelectronics

Specifications of M95512-DFCS6TP/K

• Rohs: yes

M95512-W M95512-R M95512-DR M95512-DF
5.4
5.5
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 7
with Serial Clock (C) being low.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See
detailed description of the Status Register bits.
Data protection and protocol control
The device features the following data protection mechanisms:
●
●
●
●
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
●
●
Table 2.
Status Register bits
BP1
Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
0
0
1
1
also shows what happens if the rising and falling edges are not timed to coincide
Write-protected block size
BP0
0
1
0
1
Protected block
Whole memory
Upper quarter
Upper half
none
Doc ID 11124 Rev 20
Section 6.3: Read Status Register (RDSR)
Protected array addresses
C000h - FFFFh
8000h - FFFFh
0000h - FFFFh
none
Operating features
for a
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