M95512-DFCS6TP/K STMicroelectronics, M95512-DFCS6TP/K Datasheet - Page 22

• Manufacturer Part Number: M95512-DFCS6TP/K
• Description: EEPROM 512Kb Serial Bus 2.5V to 5.5V 10MHz
• Manufacturer: STMicroelectronics

Specifications of M95512-DFCS6TP/K

• Rohs: yes

Instructions
6.5
Figure 12. Read from Memory Array (READ) sequence
22/51
S
C
D
Q
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
●
●
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●
●
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
Read from Memory Array (READ)
As shown in
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
either setting the SRWD bit after driving the Write Protect (W) input pin low,
or driving the Write Protect (W) input pin low after setting the SRWD bit.
0
1
High Impedance
2
Instruction
Figure
3
4
12, to send this instruction to the device, Chip Select (S) is first driven
5
6
7
MSB
15
8
Doc ID 11124 Rev 20
14 13
9 10
16-Bit Address
3
20 21 22 23 24 25 26 27
2
M95512-W M95512-R M95512-DR M95512-DF
1
0
MSB
7
6
5
Data Out 1
4
3
28 29 30
2
1
31
0
7
Data Out 2
AI01793D