M95512-DFCS6TP/K STMicroelectronics, M95512-DFCS6TP/K Datasheet - Page 21

• Manufacturer Part Number: M95512-DFCS6TP/K
• Description: EEPROM 512Kb Serial Bus 2.5V to 5.5V 10MHz
• Manufacturer: STMicroelectronics

Specifications of M95512-DFCS6TP/K

• Rohs: yes

M95512-W M95512-R M95512-DR M95512-DF
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes t
and AC
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t
also reset at the end of the Write cycle t
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
●
●
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
Table 6.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
signal
W
1
0
1
0
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in
The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in
Write Status Register (WRSR) instruction is not executed.
parameters).
SRWD
bit
0
0
1
1
W
Protection modes
, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
Hardware-
Software-
protected
protected
(HPM)
(SPM)
Mode
Status Register is
writable (if the WREN
instruction has set the
WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Write protection of the
Table
W
Doc ID 11124 Rev 20
Status Register
to complete (as specified in AC tables under
W
2.
Write cycle.
W
.
Table
6. When in Write-protected mode, the
Write-protected
Write-protected
Protected area
Table
6.
Memory content
(1)
Unprotected area
Ready to accept
Write instructions
Ready to accept
Write instructions
Table
Section 9: DC
Instructions
2.
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