SST85LD0512-60-RI-LBTE Greenliant, SST85LD0512-60-RI-LBTE Datasheet - Page 6

• Manufacturer Part Number: SST85LD0512-60-RI-LBTE
• Description: Flash 512MB NAND 60ns 3.3V Industrial
• Manufacturer: Greenliant

Specifications of SST85LD0512-60-RI-LBTE

• Rohs: yes
• Memory Type: NAND Flash
• Memory Size: 512 MB
• Access Time: 60 ns
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 3.3 V
• Maximum Operating Current: 85 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LBGA-88

Data Sheet
©2010 Greenliant Systems, Ltd.
Symbol
Host Side Interface
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DMACK#
DMARQ
CS1FX#
CS3FX#
CSEL
IORD#
Table 1: Pin Assignments (1 of 3)
91-TFBGA
Pin No.
H8
G9
G8
H7
G3
G2
H2
K8
K3
F9
F8
E8
F7
F4
H4
E3
H3
F3
F2
K2
L2
J3
L3
L8
L9
Type
Pin
I/O
O
I
I
I
I
I
I1Z/O2 D[15:0] Data bus
Type Name and Functions
I2U
I1U
I/O
I1Z
O1
I2Z
I2Z
512 MByte / 1 GByte / 2 GByte NANDrive
A[2:0] are used to select one of eight registers in the Task File.
DMA Acknowledge - input from host
DMA Request to host
CS1FX# is the chip select for the task file registers
CS3FX# is used to select the alternate status register and the Device
Control register.
This internally pulled-up signal is used to configure this device as a
Master or a Slave. When this pin is grounded, this device is configured
as a Master. When the pin is open, this device is configured as a
Slave. The pin setting should remain the same from Power-on to
Power-down.
IORD#: This is an I/O Read Strobe generated by the host. When Ultra
DMA mode is not active, this signal gates I/O data from the device.
HDMARDY#: In Ultra DMA mode when DMA Read is active, this sig-
nal is asserted by the host to indicate that the host is ready to receive
Ultra DMA data-in bursts. The host may negate HDMARDY# to pause
an Ultra DMA transfer.
HSTROBE: When DMA Write is active, this signal is the data-out
strobe generated by the host. Both the rising and falling edges of
HSTROBE cause data to be latched by the device. The host may stop
generating HSTROBE edges to pause an Ultra DMA data-out burst.
GLS85LD0512 / GLS85LD1001T / GLS85LD1002U
6
S71382-05-000
05/10