SST85LD0512-60-RI-LBTE Greenliant, SST85LD0512-60-RI-LBTE Datasheet - Page 7

• Manufacturer Part Number: SST85LD0512-60-RI-LBTE
• Description: Flash 512MB NAND 60ns 3.3V Industrial
• Manufacturer: Greenliant

Specifications of SST85LD0512-60-RI-LBTE

• Rohs: yes
• Memory Type: NAND Flash
• Memory Size: 512 MB
• Access Time: 60 ns
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 3.3 V
• Maximum Operating Current: 85 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LBGA-88

512 MByte / 1 GByte / 2 GByte NANDrive
GLS85LD0512 / GLS85LD1001T / GLS85LD1002U
©2010 Greenliant Systems, Ltd.
Symbol
IOWR#
IORDY
IOCS16#
INTRQ
PDIAG#
DASP#
RESET#
WP#/PD#
Serial Communication Interface (SCI)
SCID
SCID
SCICLK
Miscellaneous
V
V
V
POR#
V
SS
DD
DDQ
REG
OUT
IN
Table 1: Pin Assignments (Continued) (2 of 3)
G4, G6, G7,
K4, K6, K7,
91-TFBGA
Pin No.
E9, K5,
L5, M2
E2, M9
D9
H9
K9
E4
F6
D8
D7
E7
D2
J4
J8
J2
J9
J7
PWR
PWR
PWR
Type
Pin
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I1U/O1 The Pass Diagnostic signal in the Master/Slave handshake protocol.
I1U/O6 The Drive Active/Slave Present signal in the Master/Slave handshake
Analog
Input
Type Name and Functions
I2U
I3U
I3U
I3U
I/O
I2Z
I2Z
O2
O1
O4
1
IOWR#: This is an I/O Write Strobe generated by the host. When Ultra
DMA mode is not active, this signal is used to clock I/O data into the
device.
STOP: When Ultra DMA mode protocol is active, the assertion of this
signal causes the termination of the Ultra DMA burst
IORDY: When Ultra DMA mode DMA Write is not active and the
device is not ready to respond to a data transfer request, this signal is
negated to extend the Host transfer cycle. However, it is never
negated by this controller.
DDMARDY#: When Ultra DMA mode DMA Write is active, this signal
is asserted by the host to indicate that the device is ready to receive
Ultra DMA data-in bursts. The device may negate DDMARDY# to
pause an Ultra DMA transfer.
DSTROBE: When Ultra DMA mode DMA Read is active, this signal is
the data-out strobe generated by the device. Both the rising and falling
edges of DSTROBE cause data to be latched by the host. The device
may stop generating DSTROBE edges to pause an Ultra DMA data-
out burst.
This output signal is asserted low when the device is indicating a word
data transfer cycle.
This signal is the active high Interrupt Request to the host.
protocol.
This input pin is the active low hardware reset from the host.
The WP#/PD# pin can be used for either the Write Protect mode or
Power-down mode, but only one mode is active at any time. The Write
Protect or Power-down modes can be selected through the host com-
mand. The Write Protect mode is the factory default setting.
SCI interface data output
SCI interface data input
SCI interface clock
Ground
V
V
Power-on Reset (POR). Active Low
External capacitor pin
DD
DDQ
(3.3V)
(5V/3.3V) for Host interface
7
S71382-05-000
Data Sheet
05/10