MAX9856ATL/V+ Maxim Integrated, MAX9856ATL/V+ Datasheet - Page 20

• Manufacturer Part Number: MAX9856ATL/V+
• Description: Interface - CODECs Low-Power Audio Codec With Directdrive. Headphone Amplifiers
• Manufacturer: Maxim Integrated
• Series: MAX9856r

Specifications of MAX9856ATL/V+

• Resolution: 18 bit
• Interface Type: Serial (I2C)
• Number Of Adcs: 2
• Number Of Dacs: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Supply Current: 2.9 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V
• Thd Plus Noise: 82 dB

Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon a read operation of
Table 2. Status Registers Bit Location
Status Register Bit Description
20
HSDETR,
HSDETL,
REG
0x00
0x01
HPOCL/
HPOCR
JKSNS
JKMIC
JSDET
______________________________________________________________________________________
LSNS
JDET
CLD
SLD
ULK
BIT
GPI
Clip Detect Flag. Indicates that a signal has become clipped in the ADC.
Slew-Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through all
intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value.
Digital PLL Unlock Flag. Indicates that the digital audio PLL for the DAC or ADC has become unlocked and digital
signal data is not reliable.
Jack Microphone Flag. Indicates JACKSNS has been pulled up to the MICBIAS voltage. The microphone bias
must be enabled for this bit to function properly.
Headphone Output Left/Right Current Overload Flags. Indicate that the headphone output amplifiers have
exceeded the rated current.
Headset Configuration Change Flag. Indicates a change in JKMIC, LSNS, or JKSNS.
GPI State. Indicates the state of LRCLK_A when configured as a general-purpose input.
Headphone Sense. LSNS is set when the internal pullup current forces the voltage at HPL to exceed AVDD - 0.4V.
This indicates headphone jack insertion or removal has occurred. HPMODE must be set to 00 and JDETEN set to
1 for this bit to function.
Jack S ense. JKS N S i s set w hen the i nter nal p ul l up cur r ent for ces the vol tag e on JAC KS N S to exceed AVDD - 0.4V .
Thi s i nd i cates j ack i nser ti on or r em oval has occur r ed . JD E TE N m ust b e set for thi s b i t to functi on.
Load Impedance Sense. Indicates the approximate load connected to HPR, HPL, or JACKSNS. These bits are
updated once each time the appropriate EN bits are set high and cause an undefeatable hardware interrupt.
LSNS
CLD
B7
JKSNS
SLD
B6
Status Registers
BITS
00
01
10
11
ULK
B5
HSDETL
JKMIC
B4
the status register and are set the next time the event
occurs. Table 2 lists the status registers bit location and
description.
FUNCTION
200Ω < load < open
50Ω < load < 200Ω
0 < load < 50Ω
Idle state
HPOCL
B3
HSDETR
HEADPHONE OR JACKSNS LOAD
HPOCR
B2
JDET
B1
JSDET
GPI
B0