MAX9856ATL/V+ Maxim Integrated, MAX9856ATL/V+ Datasheet - Page 22

• Manufacturer Part Number: MAX9856ATL/V+
• Description: Interface - CODECs Low-Power Audio Codec With Directdrive. Headphone Amplifiers
• Manufacturer: Maxim Integrated
• Series: MAX9856r

Specifications of MAX9856ATL/V+

• Resolution: 18 bit
• Interface Type: Serial (I2C)
• Number Of Adcs: 2
• Number Of Dacs: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Supply Current: 2.9 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V
• Thd Plus Noise: 82 dB

Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
The MAX9856 DAC is capable of supporting any sam-
ple rate from 8kHz to 96kHz in either master or slave
mode, including all common sample rates (8kHz,
11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz,
44.1kHz, 48kHz, 88.2kHz and 96kHz).
A 15-bit clock divider coefficient must be programmed
into the device to set the DAC sample rate relative to
the prescaled MCLK input (PCLK). This allows high
flexibility in both the MCLK and LRCLK_D frequencies.
In slave mode, the interface accepts any LRCLK_D sig-
nal between 7.8kHz to 100kHz.
Table 5. DAC Interface Registers
DAC Interface Register Bit Descriptions
22
______________________________________________________________________________________
REG
0x04
0x05
0x06
REGISTER
DRATE
DWCI
DDLY
DBCI
DPLLEN
DWCI
B7
DBCI
DAC Word Clock (LRCLK_D) Invert
When PCM = 0:
0—Left-channel data is transmitted while LRCLK_D is low.
1—Right-channel data is transmitted while LRCLK_D is low.
When PCM = 1:
0—Start of a new frame is signified by the falling edge of the LRCLK_D pulse.
1—Start of a new frame is signified by the rising edge of the LRCLK_D pulse.
DAC BCLK Invert:
0—SDIN is accepted on the rising edge of BCLK.
1—SDIN is accepted on the falling edge of BCLK.
In master mode:
0—LRCLK_D transitions occur on the falling edge of BCLK.
1—LRCLK_D transitions occur on the rising edge of BCLK.
DAC Modulator Rate:
00—Low-power mode
01—Reserved
10—High-performance mode
11—DAC clock disabled
DAC Data Delay:
0—The most significant bit of an audio word is latched at the first BCLK edge after the
LRCLK_D transition.
1—The most significant bit of an audio word is latched at the second BCLK edge after the
LRCLK_D transition.
(DDLY = 1 for I
B6
DAC Interface
B5
2
S-compatible mode)
DRATE
B4
There are two speed settings for the DAC set by the
DRATE control bits. The highest rate runs the modulator
at an internal clock rate between 5MHz and 10MHz,
and provides the highest audio performance. The low
rate runs the modulator between 2.5MHz and 5MHz for
reduced power consumption.
The digital audio interface offers full functionality for
several digital audio formats including left-justified, I
and PCM modes (Figure 1). Figure 2 shows the digital
timing for various modes. Table 5 shows the DAC inter-
face registers and descriptions. Table 6 lists the common
DACNI and ADCNI values.
DACNI[7:0]
DDLY
DACNI[14:8]
B3
FUNCTION
PCM
B2
DHF
B1
WS
B0
2
S,