FT240XS-U FTDI, FT240XS-U Datasheet - Page 15

• Manufacturer Part Number: FT240XS-U
• Description: USB Interface IC USB to Parallel FIFO IC SSOP-24
• Manufacturer: FTDI

Specifications of FT240XS-U

• Rohs: yes
• Tradename: X-Chip

FT240X USB 8-BIT FIFO IC Datasheet
Version 1.3
FTDI# 259
Document No.: FT_000626 Clearance No.:
4.2 Functional Block Descriptions
The following paragraphs detail each function within the FT240X. Please refer to the block
diagram shown in Figure 2.1
.
Internal MTP Memory. The internal MTP memory in the FT240X is used to store USB Vendor ID (VID),
Product ID (PID), device serial number, product description string and various other USB configuration
descriptors. The FT240X is supplied with the internal MTP memory pre-programmed as described in
Section 8. A user area of the internal MTP memory is available to system designers to allow storing
additional data from the user application over USB. The internal MTP memory descriptors can be
programmed in circuit, over USB without any additional voltage requirement. The descriptors can be
programmed using the FTDI utility software called FT_PROG, which can be downloaded from FTDI Utilities
on the FTDI website (www.ftdichip.com).
+1.8V LDO Regulator. The +1.8 LDO regulator generates the +1.8V reference voltage for driving the
internal core of the IC.
+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the
USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the
3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on
USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells
rather than to power external logic. However, it can be used to supply external circuitry requiring a
+3.3V nominal supply with a maximum current of 50mA.
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface
to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential
input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB
reset detection conditions respectfully. This function also incorporates a 1.5kΩ pull up resistor on USBDP.
The block also detects when connected to a USB power supply which will not enumerate the device but
still supply power and may be used for battery charging.
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock
and data signals for the Serial Interface Engine (SIE) block.
Internal 12MHz Oscillator. The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This
provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference
clock for the SIE, USB Protocol Engine and FIFO controller blocks.
Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal
Oscillator function and generates the 48MHz. The 48Mz clock reference is used by the USB DPLL and the
Baud Rate Generator blocks.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial
and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also verifies the CRC on the USB data
stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol requests generated by the USB host controller and the
commands for controlling the functional parameters of the FIFO in accordance with the USB 2.0
specification Section 9.
FIFO RX Buffer (512 bytes). Data sent from the USB host controller to the FIFO via the USB data OUT
endpoint is stored in the FIFO RX (receive) buffer and is removed from the buffer by reading the contents
of the FIFO using the RD# pin. (Rx relative to the USB interface).
FIFO TX Buffer (512 bytes). Data written into the FIFO using the WR pin is stored in the FIFO TX
(transmit) Buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB
request for data from the device data IN endpoint. (Tx relative to the USB interface).
FIFO Controller with Programmable High Drive. The FIFO Controller handles the transfer of data
between the FIFO RX, the FIFO TX buffers and the external FIFO interface pins (D0 - D7).
Additionally, the FIFO signals have a configurable high drive strength capability which is configurable in
the MTP memory.
RESET Generator. The integrated Reset Generator Cell provides a reliable power-on reset to the device
internal circuitry at power up. The RESET# input pin allows an external device to reset the FT240X.
RESET# can be tied to VCC or left unconnected if not being used.
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