C8051F305-GSR Silicon Labs, C8051F305-GSR Datasheet - Page 128

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C8051F305-GSR

Manufacturer Part Number
C8051F305-GSR
Description
8-bit Microcontrollers - MCU 2KB 14Pin MCU
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F305-GSR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F300/1/2/3/4/5
128
1000
0100
0101
Values Read
1
0
0
0
0
X
0
0
0
1
Table 13.4. SMBus Status Decoding (Continued)
X A master data byte was received;
X A Slave byte was transmitted;
X An illegal STOP or bus error was
0 A slave byte was transmitted;
1 A slave byte was transmitted;
ACK requested.
NACK received.
ACK received.
error detected.
detected while a Slave Transmis-
sion was in progress.
Current SMbus State
Rev. 2.9
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last
byte, and send STOP.
Send NACK to indicate last
byte, and send STOP fol-
lowed by START.
Send ACK followed by
repeated START.
Send NACK to indicate last
byte, and send repeated
START.
Send ACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
Send NACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
No action required (expect-
ing STOP condition).
Load SMB0DAT with next
data byte to transmit.
No action required (expect-
ing Master to end transfer).
Clear STO.
Typical Response Options
0
0
1
1
1
0
0
0
0
0
0
Written
Values
0
1
1
0
0
0
0
0
0
0
0
X
X
X
X
1
0
0
1
0
1
0

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