FM24C256B-G Cypress Semiconductor, FM24C256B-G Datasheet - Page 6

• Manufacturer Part Number: FM24C256B-G
• Description: F-RAM 256Kb Serial I2C 5V FRAM
• Manufacturer: Cypress Semiconductor

Specifications of FM24C256B-G

• Rohs: yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 85 C

Read Operation
There are two types of read operations. They are
current address read and selective address read. In a
current address read, the FM24C256 uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to set the address
to a specific value.
Current Address & Sequential Read
As mentioned above the FM24C256 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a device address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving
FM24C256 will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte, the internal address
counter will be incremented.
Each time the bus master acknowledges a byte, this
indicates that the FM24C256 should read out the next
sequential byte.
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
Rev. 3.3
Jan. 2011
By FM24C256
By Master
By FM24C256
By Master
Start
S
the
Slave Address
complete
Start
S
Slave Address 0
0
device
A
X
Address & Data
Address MSB
address,
A
Figure 6. Multiple Byte Write
Figure 5. Single Byte Write
X
Acknowledge
Address & Data
Address MSB
the
A
Address LSB
Acknowledge
A
most likely create a bus contention as the FM24C256
attempts to read out additional data onto the bus. The
four valid methods are as follows.
1.
2.
3.
4.
If the internal address reaches 7FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the device address with the lsb set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM24C256 acknowledges the address, the bus master
issues a Start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the device address LSB set to a 1. The
operation is now a current address read.
The bus master issues a no-acknowledge in the
9
This is illustrated in the diagrams below. This is
preferred.
The bus master issues a no-acknowledge in the
9
The bus master issues a stop in the 9
cycle.
The bus master issues a start in the 9
cycle.
Address LSB
th
th
A
clock cycle and a start in the 10
clock cycle and a stop in the 10
Data Byte
A
Data Byte
A
Data Byte
A
th
th
Stop
.
P
FM24C256
clock cycle.
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th
th
A
Stop
clock
clock
P