FM25L256-GC Cypress Semiconductor, FM25L256-GC Datasheet

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FM25L256-GC

Manufacturer Part Number
FM25L256-GC
Description
F-RAM 256K (32Kx8) 2.7V
Manufacturer
Cypress Semiconductor
Datasheet

Specifications of FM25L256-GC

Product Category
F-RAM
Rohs
yes
Memory Size
256 KB
Organization
32 K x 8
Interface
SPI
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
0 C to + 70 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Factory Pack Quantity
100
Pre-Production
FM25L256
256Kb FRAM Serial 3V Memory – Commercial Temp.
Features
256K bit Ferroelectric Nonvolatile RAM
Very Fast Serial Peripheral Interface - SPI
Description
The FM25L256 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM25L256 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array
immediately after each byte has been transferred to
the device. The next bus cycle may commence
without the need for data polling. In addition, the
product offers virtually unlimited write endurance.
FRAM also exhibits much lower power consumption
than EEPROM.
These capabilities make the FM25L256 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
The FM25L256 provides substantial benefits to users
of
replacement. The FM25L256 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. Device specifications are
guaranteed over a commercial temperature range of
0°C to +70°C.
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change the
specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Rev. 2.4 (obsolete)
Feb. 2009
Organized as 32,768 x 8 bits
Unlimited Read/Write Cycles
10 Year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Up to 25 MHz Frequency
Direct Hardware Replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
serial
level
EEPROM
reliability
as
problems
a
hardware
caused
drop-in
by
Write Protection Scheme
Low Power Consumption
Industry Standard Configurations
Pin Configuration
Ordering Information
FM25L256-SC
FM25L256-GC
FM25L256-DGC
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Hardware Protection
Software Protection
Low Voltage Operation 2.7V – 3.6V
1 A (typ) Standby Current
Commercial Temperature 0 C to +70 C
8-pin SOIC and 8-pin TDFN Packages
“Green” Packaging Options
VSS
WP
SO
CS
1850 Ramtron Drive, Colorado Springs, CO 80921
VSS
/WP
/CS
SO
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (2.7 to 3.6V)
Ground
1
2
3
4
1
2
3
4
Ramtron International Corporation
Top View
8-pin SOIC
“Green” 8-pin SOIC
“Green” 8-pin TDFN
(800) 545-FRAM, (719) 481-7000
8
7
6
5
8
7
6
5
VDD
/HOLD
SCK
SI
www.ramtron.com
VDD
HOLD
SCK
SI
Page 1 of 14

Related parts for FM25L256-GC

FM25L256-GC Summary of contents

Page 1

... Packaging Options Pin Configuration caused by VSS /CS SO /WP VSS Pin Name /CS /WP /HOLD SCK SI SO VDD VSS drop-in Ordering Information FM25L256-SC FM25L256-GC FM25L256-DGC 1850 Ramtron Drive, Colorado Springs, CO 80921 VDD 1 8 HOLD 2 7 SCK VDD /HOLD SCK ...

Page 2

... SO may be connected to SI for a single pin data interface. VDD Supply Power Supply (2.7V to 3.6V) VSS Supply Ground Rev. 2.4 (obsolete) Feb. 2009 Clock Generator Control Logic Write Protect 8192 x 32 FRAM Array 15 Address Register Counter Data I/O Register Nonvolatile Status Figure 1. Block Diagram specifications. DD FM25L256 Commercial Temp Register Page ...

Page 3

... This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25L256 due to its fast write cycle and high endurance as compared to EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...

Page 4

... Rev. 2.4 (obsolete) Feb. 2009 SO SI SCK SO FM25L256 FM25L256 CS HOLD CS P1.0 P1 FM25 L256 C S HOLD P1 Figure 4. SPI Modes 0 & 3 FM25L256 Commercial Temp. SI SCK HOLD MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select SCK Page ...

Page 5

... Power Up to First Access The FM25L256 is not accessible for a period of time (10 ms) after power up. Users must comply with the timing parameter t , which is the minimum time PU from V (min) to the first /CS low. DD Data Transfer All data transfers to and from the FM25L256 occur in 8-bit groups. They are synchronized to the clock signal (SCK), and they transfer most significant bit (MSB) first ...

Page 6

... Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR op- code, the FM25L256 will return one byte with the contents of the Status register. The Status register is described in detail in a later section. ...

Page 7

... The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus EEPROMs, the FM25L256 can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code ...

Page 8

... MSB LSB Figure 9. Memory Write 16-bit Address MSB LSB Figure 10. Memory Read FM25L256 Commercial Temp Data MSB LSB Data Out ...

Page 9

... Std JESD22-A115-A) = 2.7V to 3.6V unless otherwise specified) DD Min Typ 2 0 -0.3 V – other inputs -0.3V FM25L256 Commercial Temp. Ratings -1.0V to +5.0V -1.0V to +5.0V and V < V +1. - 125 C 300 C 3kV 1kV 100V MSL-1 Max Units Notes 3 0 1.0 A 2 ...

Page 10

... DD min) DD waveform. power ramp profiles. The behavior of the internal circuits is difficult to predict DD = 3.3V) DD Min - - DD DD FM25L256 Commercial Temp. = 3.0 to 3.6V DD Min Max Units Notes 0 25 MHz ...

Page 11

... SI SO /Hold Timing CS SCK HOLD SO Power Cycle Timing Data Retention (V = 2.7V to 3.6V) DD Parameter Data Retention Rev. 2.4 (obsolete) Feb. 2009 tCL tF tR tOH tODV tHS tHH tHS tHZ Min Max Units 10 - Years FM25L256 Commercial Temp. tD tCSH tCH tOD tHH tLZ Notes Page ...

Page 12

... Legend: XXXX= part number, P= package (S, G, DG), T= temp (C=comm., blank=ind.) LLLLLLL= lot code XXXXXXPT RIC=Ramtron Int’l Corp, YY=year, WW=work week LLLLLLL RICYYWW Example: FM25L256, Standard SOIC package, Commercial temperature, Year 2005, Work Week 39 FM25L256SC A40003S RIC0539 Rev. 2.4 (obsolete) Feb. 2009 Recommended PCB Footprint 3 ...

Page 13

... R=Ramtron, G=”green” TDFN package, XXXX=base part number RGXXXX LLLL= lot code, T= temperature (C=commercial, blank=extended) LLLL_T YY=year, WW=work week YYWW Example: “Green” TDFN package, FM25L256, Commercial temperature, Lot 0003, Year 2005, Work Week 39 RG5L25 0003_C 0539 Rev. 2.4 (obsolete) Feb. 2009 Exposed metal pad ...

Page 14

... Split into commercial and industrial datasheets. Added recommended pcb footprint to DFN package drawing. Changed DFN marking scheme. Added power up note to Power Cycle Timing table. Package name change, from DFN to TDFN. Not recommended for new designs. Use FM25L256B as an alternative. Changed status to obsolete. FM25L256 Commercial Temp. spec limit. Changed t ...

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