GLS85LD0512-60-RI-LBTE (Rev AC0) Greenliant, GLS85LD0512-60-RI-LBTE (Rev AC0) Datasheet - Page 2

• Manufacturer Part Number: GLS85LD0512-60-RI-LBTE (Rev AC0)
• Description: Memory Controllers 512MB NAND 60ns 3.3V Industrial
• Manufacturer: Greenliant

Specifications of GLS85LD0512-60-RI-LBTE (Rev AC0)

• Rohs: yes
• Battery Backup Switching: No
• Description/function: High-performance, fully-integrated, embedded flash solid-state drive
• Lithium Battery Monitor: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 85 mA

1.0
Each PATA NANDrive contains an integrated PATA NAND flash memory controller and discrete NAND flash
die(s) in a LBGA package. Refer to Figure 2-1 for the PATA NANDrive block diagram.
1.1
The heart of the PATA NANDrive is the PATA NAND
flash memory controller, which translates standard
PATA signals into flash media data and control
signals. The following components contribute to the
PATA NANDrive’s operation.
1.1.1
The MCU transfers the ATA/IDE commands into data
and control signals required for flash media operation.
1.1.2
The PATA NANDrive uses internal DMA allowing
instant data transfer from/to buffer to/from flash media.
This
overhead associated with the traditional, firmware-
based approach, thereby increasing the data transfer
rate.
1.1.3
The PMU controls the power consumption of the
PATA NANDrive. The PMU dramatically reduces the
power consumption of the PATA NANDrive by putting
the part of the circuitry that is not in operation into
sleep mode.
1.1.4
A key contributor to the PATA NANDrive performance
is an SRAM buffer. The buffer optimizes the Host’s
data transfer to and from the flash media.
1.1.5
The embedded flash file system is an integral part of
the PATA NANDrive. It contains MCU firmware that
performs the following tasks:
These specifications are subject to change without notice.
© 2012 Greenliant Systems
GLS85LD1001T / GLS85LD512
Industrial Grade PATA NANDrive™
1. Translates host side signals into flash media
2. Provides flash media wear leveling to spread the
3. Keeps track of data file structures
writes and reads
flash writes to increase the longevity of flash
media
implementation
GENERAL DESCRIPTION
Optimized PATA NANDrive
Microcontroller Unit (MCU)
Internal Direct Memory Access (DMA)
Power Management Unit (PMU)
SRAM Buffer
Embedded Flash File System
eliminates
microcontroller
2
1.1.6
High performance is achieved through optimized
hardware error detection and correction.
1.1.7
The Serial Communication Interface (SCI) is designed
for manufacturing error reporting. During the design
process, always provide access to the SCI port in the
PCB design to aid in design validation.
1.1.8
The multi-tasking interface enables fast, sustained
write performance by allowing concurrent Read,
Program and Erase operations to multiple flash media
devices.
1.2
Advanced NAND management technology balances
the wear on erased blocks with an advanced wear-
leveling scheme. Advanced NAND management
technology tracks the number of program/erase cycles
within a group. When the Host updates data, higher
priority is given to the less frequently written erase
blocks; thereby, evenly distributing host writes within a
wear-leveling group.
Advanced NAND management technology enhances
the PATA NANDrive security with password protection
and four independent protection zones, which can be
set to Read-only or Hidden.
Error Correction Code (ECC)
Serial Communication Interface (SCI)
Multi-tasking Interface
Advanced NAND Management
Fact Sheet 01.000
October 2012
10/30/2012
S71382-F