GLS85LD0512-60-RI-LBTE (Rev AC0) Greenliant, GLS85LD0512-60-RI-LBTE (Rev AC0) Datasheet - Page 5

• Manufacturer Part Number: GLS85LD0512-60-RI-LBTE (Rev AC0)
• Description: Memory Controllers 512MB NAND 60ns 3.3V Industrial
• Manufacturer: Greenliant

Specifications of GLS85LD0512-60-RI-LBTE (Rev AC0)

• Rohs: yes
• Battery Backup Switching: No
• Description/function: High-performance, fully-integrated, embedded flash solid-state drive
• Lithium Battery Monitor: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 85 mA

Table 3-1: Pin Assignments (2 of 2)
These specifications are subject to change without notice.
© 2012 Greenliant Systems
Serial Communication Interface (SCI)
Miscellaneous
GLS85LD1001T / GLS85LD512
Industrial Grade PATA NANDrive™
WP#/PD#
IOCS16#
RESET#
SCID
Symbol
PDIAG#
SCICLK
DASP#
IORDY
INTRQ
SCID
POR#
V
V
DNU
V
V
DDQ
REG
SS
DD
OUT
IN
G4, G6, G7, K4,
L4, L6, L7, M3,
E9, K5, L5, M2
B10, D3, D4,
A10, B1, B9,
M4, M5, M6,
R9, R10, T1,
M7, M8, N2,
D5, D6, E5,
E6, F5, G5,
N3, N4, N5,
N6, N7, N8,
N9, R1, R2,
T2, T9, T10
A1, A2, A9,
K6, K7, J9
Pin No.
91-Ball
E2, M9
K9
D9
E4
D8
D7
E7
D2
F6
J4
J8
J2
J7
Type
PWR
PWR
PWR
Pin
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I/O Type
I1U/O1
I1U/O6
Analog
Input
I2U
I3U
I3U
I3U
O1
O2
O1
O4
Do not use. All these pins should not be connected.
IORDY: When in PIO mode, the device is not ready to respond to a
data transfer request. This signal is negated to extend the Host
transfer cycle from the assertion of IORD# or IOWR#. However, it is
never negated by this controller. (This pin supports three functions)
DDMARDY#: When Ultra DMA mode DMA Write is active, this signal
is asserted by the device to indicate that the device is ready to
receive Ultra DMA data-out bursts. The device may negate
DDMARDY# to pause an Ultra DMA transfer.
DSTROBE: When Ultra DMA mode DMA Read is active, this signal is
the data-in strobe generated by the device. Both the rising and falling
edges of DSTROBE cause data to be latched by the Host. The device
may stop generating DSTROBE edges to pause an Ultra DMA data-in
burst.
This output signal is asserted low when the device is indicating a
Word data transfer cycle.
This signal is the active high Interrupt Request to the Host.
The Pass Diagnostic signal in the Master/Slave handshake protocol.
The Drive Active/Slave Present signal in the Master/Slave handshake
protocol.
This input pin is the active low hardware reset from the Host.
The WP#/PD# pin can be used for either the Write Protect mode or
Power-down mode, but only one mode is active at any time. The
Write Protect or Power-down modes can be selected through the host
command. The Write Protect mode is the factory default setting.
SCI data output. No external pull-up or pull-down resistor should
connect to this signal.
SCI data input
SCI clock
Ground
V
V
Power-on Reset (POR). Active low. Analog input for supply voltage
detection
External capacitor pin
DD
DDQ
(3.3V)
(5V/3.3V) for Host interface
5
Name and Functions
Fact Sheet 01.000
October 2012
10/30/2012
S71382-F